to comply with the UK GOV National Security Vetting Procedures (see link below); gov.uk/government/organisations/united-kingdom-security-vetting Advantageous Cadence toolset experience Regulatory qualification (EMC, safety) of electronic products Understanding of power supply design. Understanding of signal integrity for high-speed digital design. Understanding More ❯
Relevant work experience • An enthusiasm to learn new skills Ability to comply with the UK GOV National Security Vetting Procedures (see link below); Advantageous • Cadence toolset experience • Regulatory qualification (EMC, safety) of electronic products • Understanding of power supply design. • Understanding of signal integrity for high-speed digital design. • Understanding More ❯
the UK GOV National Security Vetting Procedures (see link below); https://www.gov.uk/government/organisations/united-kingdom-security-vetting Advantageous • Cadence toolset experience • Regulatory qualification (EMC, safety) of electronic products • Understanding of power supply design. • Understanding of signal integrity for high-speed digital design. • Understanding More ❯
documentation and support the transition to manufacturing. Support & Solve : Assist in developing production test strategies and troubleshooting manufacturing issues. What you bring: Mastery of Cadence Allegro/OrCAD tools. Experience with high-speed SERDES (28G/56G PAM4). Knowledge of power electronics, especially DC-DC converters. Familiarity with More ❯
mitigation. Also, has experience with desense mitigation with integrated PMUs/DSPs (i.e. substrate isolation, return loops, package isolation, frequency planning, etc)Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).Extensive experience in Silicon More ❯
Edinburgh, Scotland, United Kingdom Hybrid / WFH Options
Cirrus Logic
latch-up requirements, physical verification, and characterization Chip-level ESD signoff experience Must understand layout and be able to guide layout engineers Proficiency with Cadence schematic capture, layout, and simulation tools Ability to work independently and lead or be part of a technical team Effective oral and written communication More ❯
Requirements include: A University degree within Electronic Engineering or related field Experience of designing MEMS devices and test structures Experience within simulation (Spice/Cadence/Matlab) would be desirable Experience using COMSOL/FEA would also be preferred. A competitive salary is on offer, together benefits including pension More ❯
to translate system-level requirements into efficient and reliable RTL using Verilog. The role is hands-on and will involve extensive work within the Cadence toolchain. Key Responsibilities: Develop synthesizable Verilog RTL for core digital blocks interfacing with TMR-based analog front ends and system controllers Collaborate with the … ASIC and sensor system designers to define block-level specifications Perform RTL simulation and functional verification using Cadence tools Support ASIC tape-out flow and post-silicon bring-up alongside test engineers Contribute to system integration with embedded software and mixed-signal components Document design specifications, verification plans, and … in Verilog HDL and digital design fundamentals Understanding of RTL to GDS signoff flow (STA, clock tree synthesis, DFT etc.) Hands-on experience with Cadence tools Solid understanding of clock domain crossing, low-power design (UPF), and bus protocols Strong documentation and communication skills, with the ability to engage More ❯