Technical Lead
Cardiff, Wales, United Kingdom
IC Resources
synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital tools for synthesis, STA, and DFT. Lead design reviews and help establish design methodologies and best practices. Support tape-out and lab-based silicon validation. Mentor junior engineers … design with a strong background in AI/ML hardware, compute, or DSP architectures. Deep understanding of SoC architecture, PPA trade-offs, and modern design flows. Confident user of Cadence tools and design environments. Prior experience leading or mentoring engineering teams. Must have the right to work in the UK and be available on-site several days per week. More ❯
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