1 of 1 Code Coverage Jobs in Reading

digital subsystems and mixed-signal ICs. Your work will include: Developing SystemVerilog/UVM verification environments Verification planning and test development Constrained-random and coverage-driven verification SVA/assertions Functional and code coverage RTL and testbench debugging Verification methodology and infrastructure improvements Working closely with design … ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in: SystemVerilog | UVM | SVA | Constrained Random Verification | Functional Coverage | RTL Debug Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation or scripting would be particularly valuable. Why consider ...