6 of 6 Code Coverage Jobs in Scotland

seeking experienced Verification Engineers to ensure the functional correctness and robustness of complex AI accelerator designs. You will play a key role in developing advanced verification environments and driving coverage closure to achieve first-silicon success. Key Responsibilities Collaborate with design and architecture teams to define and implement verification strategies for AI accelerator blocks and SoC subsystems. Build scalable … SystemVerilog/UVM testbenches, including test plans, monitors, checkers, scoreboards, and constrained-random stimulus. Perform coverage-driven and assertion-based verification, analyse coverage reports, and close functional and code coverage gaps. Debug complex hardware–software interactions, reproduce silicon issues in simulation, and work closely with RTL, architecture, and software engineers to resolve them. Develop verification frameworks More ❯

and implement eligibility rules using CER (Curam Express Rules). Design and implement workflows for deferred processing. Create/maintain technical documentation. Write Junit Tests for unit testing and code coverage. Support bug fixes during testing and deploy to target environments. Required Technical and Professional Expertise Developers are well versed in Some UML Modelling, XML, Java and the following More ❯

MEng/MSc Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience More ❯

MEng/MSc Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience More ❯

MEng/MSc Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience More ❯

MEng/MSc Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience More ❯