Bristol. In this hands-on technical role, you will contribute to a variety of SoC, subsystem, and IP development projects, taking responsibility for the verification process from planning to coverage closure. Working closely with ASIC/SoC project leaders, you will architect, specify, and lead the implementation of high-level verification projects, using advanced verification languages. You will also … Desirable: A Master's or PhD in a related subject, with 5+ years of practical experience. Skills & Experience: Essential: Proven experience in metric-driven verification, including verification planning, functional coverage, codecoverage, unit-level verification, and top-level verification. Expertise in testbench architecture design and hands-on experience with System Verilog, UVM, ABV, and constrained random verification. More ❯
and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. Manage functional and codecoverage metrics to track and report progress. Troubleshoot, debug, and resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM More ❯
and maintain verification infrastructure in collaboration with design teams and external partners. Define and implement detailed verification strategies and architectures to ensure product quality and performance. Manage functional and codecoverage metrics to track and report progress. Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM More ❯
MEng/MSc Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and codecoverage analysis SystemVerilog - SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Scripting experience More ❯
Newbury, Berkshire, United Kingdom Hybrid / WFH Options
Cirrus Logic
discipline. Proven track record in delivering 1st time success with complex mixed signal IC's. Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and codecoverage analysis SystemVerilog - SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Strong ability More ❯
