Design Verification Engineer
Edinburgh, Scotland, United Kingdom
IC Resources
AI accelerator designs. You will play a key role in developing advanced verification environments and driving coverage closure to achieve first-silicon success. Key Responsibilities Collaborate with design and architecture teams to define and implement verification strategies for AI accelerator blocks and SoC subsystems. Build scalable SystemVerilog/UVM testbenches, including test plans, monitors, checkers, scoreboards, and constrained-random … and assertion-based verification, analyse coverage reports, and close functional and code coverage gaps. Debug complex hardware–software interactions, reproduce silicon issues in simulation, and work closely with RTL, architecture, and software engineers to resolve them. Develop verification frameworks that scale across unit-level simulation, emulation, and post-silicon validation, incorporating high-level models and test generators. Qualifications Proven … preferably with exposure to CPU, GPU, NPU, or AI accelerator IP. Strong skills in SystemVerilog, UVM, and scripting languages such as Python, C++, Perl, or TCL. Solid understanding of computer architecture, memory hierarchies, and standard interconnects (e.g., AMBA/AXI, NoC). Familiarity with formal verification, assertion-based methodologies, and low-power verification techniques is a plus. Ability More ❯
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