3 of 3 Design Engineer Jobs in Farnborough

Senior Physical Design Engineer

Hiring Organisation
IC Resources
Location
Farnborough, England, United Kingdom
Senior Physical Design Engineer - Farnborough A leading international space technology organisation is continuing to expand its advanced ASIC capability and is seeking a Senior Physical Design Engineer to support the development of complex satellite SoCs. This opportunity sits within our client’s semiconductor division, focused … team works on technically demanding mixed-signal ASICs in advanced technology nodes, including devices designed for high-reliability environments. As a Senior Physical Design Engineer, you will contribute across the full physical implementation cycle, from RTL handoff through to tape-out and production. You will take ownership ...

Analog Design Engineer

Hiring Organisation
eTeam Workforce Limited
Location
Farnborough, Hampshire, United Kingdom
Employment Type
Contract
Contract Rate
GBP Annual
Title: Analogue Design Engineer location: Farnborough Contract: 8 Months Job Overview - Dept Description and Job Duties: The senior engineer will take on the design of multiple analogue blocks including LDOs, temperature sensors, central biasing, test bus and process monitors. The tasks will include: Review of block … specifications and architecture selection. Schematic design, simulation and reporting compliance to specifications. Overseeing a layout engineer to complete the layout. Post-layout parasitic simulation and necessary adjustments. Documentation of usage and any calibrations etc. Liaising with the chip lead to integrate the designs. Presentation of design ...

Analog IC Design Engineer

Hiring Organisation
eTeam Workforce Limited
Location
Farnborough, Hampshire, United Kingdom
Employment Type
Contract
Contract Rate
GBP Annual
Title: Analog IC Design Engineer Location: Farnborough, UK Job Type: Full-time, Unit November 2026 Work Model: Hybrid Summary: The senior engineer will take on the design of multiple analogue blocks including LDOs, temperature sensors, central biasing, test bus and process monitors. The tasks will include … Review of block specifications and architecture selection. Schematic design, simulation and reporting compliance to specifications. Overseeing a layout engineer to complete the layout. Post-layout parasitic simulation and necessary adjustments. Documentation of usage and any calibrations etc. Liaising with the chip lead to integrate the designs. Presentation ...