collaborate with multi-site development teams and customers to propose solutions and ensure the delivery of high-quality verification environments and methodologies. If you are a passionate and innovative engineer who enjoys solving complex verification problems and leading teams, this could be the perfect opportunity for you. Key Responsibilities: Verification Expertise: Provide hands-on expertise in IP and SoC … remains at the forefront of industry best practices. Cross-Functional Collaboration: Coordinate with cross-functional teams to define verification strategies and create comprehensive verification plans for SoC designs. Optimised Design Solutions: Deliver cutting-edge, optimised solutions for functional verification, ensuring high-quality outcomes. Recruitment Support: Contribute to the recruitment process by interviewing candidates and assisting in team expansion activities. … Key Relationships: Internal: Reports to: Engineering Manager/Principal Engineer Collaborates with: Engineers, Senior Engineers, Principal Engineers, Project Managers, and HR teams External: Suppliers: EDA Tool Vendors, Foundries, and Assembly Houses Qualifications: A degree, Master's, or PhD in a relevant subject. Typically, 5+ years of experience in SoC , subsystem , or IP verification in a team environment. A Master More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems … for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems … for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯
