1 of 1 Electronic Design Automation Jobs in Bath

components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification … experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯