3 of 3 Electronic Design Automation Jobs in Bristol

RTL/ASIC Design Engineer 📍 Bristol or Cambridge | 3 days onsite per week 💰 Leading compensation & benefits package This is a superb opportunity to join one of the hottest names in the semiconductor industry — building technology that’s transforming the future of AI and humanity itself. You’ll work on world-class products that set the standard in made-for … revolution. Although this is an individual contributor role, there’s a clear career path with progression into technical leadership or managerial positions if desired. Role Overview As an ASIC Design Engineer in the Logical Design team, you’ll contribute to high-quality micro-architecture specifications and RTL for advanced silicon products. You’ll also collaborate across the wider … to ensure successful delivery of cutting-edge chips. Responsibilities Deliver high-quality micro-architecture specifications and RTL. Contribute to shared design infrastructure and flows. Work with industry-leading EDA tools and design methodologies. Support block-level and chip-level verification, including linting, synthesis, timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering More ❯

and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer … The Person: Degree in a technical field such as Electrical/Electronic Engineering, Mathematics, Physics, Computing, or Robotics Experienced in SystemVerilog and UVM verification methods Experienced in using EDA tools Reference: BBBH21987 Keywords: SVUVM, UVM, SV UVM, Specman-e, Functional Coverage, Testbench Development, Debugging, EDA Tools, Python, Scripting, IP Verification, Bristol, Hybrid If you're interested in this role More ❯

and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored development plans, and support to enhance your technical expertise, strengthen your understanding of EDA tools, and progress toward more senior verification roles as your experience grows. This is a full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week … term career progression and the opportunity to boost earnings through a company bonus. The Role: Develop and maintain SystemVerilog - UVM test benches with full training and guidance Support the design and integration of new verification components Monday to Friday, 09:00AM - 17:00PM, with two days per week … working from home The Person: Degree in Electrical/Electronic Engineering, Mathematics, Physics, Computing, or Robotics Some experience or interest in SystemVerilog and UVM verification methods Familiarity with EDA tools or scripting languages Reference: BBBH21987 Keywords: SVUVM, UVM, SV UVM, Specman-e, Functional Coverage, Testbench Development, Debugging, EDA Tools, Python, Scripting, IP Verification, Bristol, Hybrid If you're interested More ❯