5 of 5 Electronic Design Automation Jobs in the South West

other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others. Interface with foundries and process engineers to ensure manufacturability and yield optimisation. Work closely … related field. 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below). Strong proficiency in EDA tools for place & route, STA, and sign-off. Solid understanding of CMOS technology, semiconductor physics, and process limitations. Experience with low-power design methodologies, power ...

against project plans.· Definition of verification strategy, planning and execution and new verification methodology and clear documentation thereof.· Trialling and deployment of industry-leading EDA tools for verification quality, efficiency, execution and metric analysis.· Track development activities and administer milestones deliverables.· Collate engineering data and provide regular feedback to customers … Formal verification apps - x-prop, connectivity,CDC· Formal FPV· System-wide cache management, coherent and non-coherent NoC verification· Understanding of AI application in EDA process· Power aware verification – UPF and or CPF· gate-level simulation with SDF· SoC level verification – HW/SW co-verification, multi-mode simulation· Understanding ...

neural accelerators is accelerating rapidly — and this company is at the forefront of that evolution. They are now looking for an experienced ASIC Design Engineer to join their Fabric IP team, bringing deep expertise in microarchitecture and RTL design to help shape the future of their technology portfolio. … Electrical Engineering, Computer Engineering, or Computer Science 8+ years of hands‐on experience in microarchitecture and RTL development Solid understanding of industry‐standard EDA tools and design methodologies Deep knowledge of on‐chip interconnects and NoCs Experience with cache coherency, memory subsystems, interconnects, or NoC IP is highly desirable ...

Senior Physical Design Engineer - Bristol An innovative semiconductor company is seeking a Senior Physical Design Engineer to support the delivery of next-generation, low-power Wi-Fi SoCs used in high-volume consumer devices. This is a key backend position with real ownership across the full implementation cycle … timing closure methodologies and sign-off requirements Experience with low-power implementation for battery-operated or power-sensitive designs Familiarity with industry-standard EDA tools and scripting (Tcl, Python, Shell or similar) Ability to take ownership of complex technical challenges in a fast-paced development environment This Senior Physical Design ...

Physical Design Engineer to drive innovative chip designs. Candidates should possess 7+ years of experience in physical design with strong proficiencies in EDA tools, a solid understanding of CMOS technology, and excellent problem-solving and communication skills. This hybrid position offers the chance to be a part ...