2 of 2 FPGA Design Jobs in Central London

Silicon Design Engineer Overview: Join a cutting-edge technology team shaping next-generation mobile, smart, and connected solutions. As a Silicon Design Engineer , you’ll design, optimize, and debug complex hardware modules, ensuring high performance, efficiency, and reliability. Responsibilities: Develop and optimize digital silicon designs in collaboration with verification and validation teams. Define microarchitecture … specifications and execution plans. Balance performance trade-offs (speed, power, area) through in-depth analysis. Participate in design reviews and contribute to a high-quality design environment. Utilize industry-leading tools and methodologies to enhance silicon design. About You: You are a proactive problem solver with a strong technical background in silicon design. A skilled communicator … collaborator, you thrive in a fast-paced, innovative environment. Required Skills: Expertise in digital IC design and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU More ❯

ASIC Lead (Digital) who can drive a complex, high‐speed mixed‐signal chip from concept to mass production while line‐managing and mentoring a world‐class team of design engineers. You will own delivery of the digital subsystems that stitch together > 100 high‐bandwidth lanes, interface to fast‐settling DACs and ADCs, and run deterministic control loops at … DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical design ► sign‐off. Lead and line‐manage 6‐12 digital & mixed‐signal engineers: goal‐setting, performance reviews, recruiting, and skills development and maintain a culture of rapid, first‐time‐right … and clock‐mesh networks to guarantee end‐to‐end timing determinism and low‐latency control loops. Drive design verification strategy —UVM test‐benches, gate‐level sims, FPGA prototyping—and own silicon bring‐up test plans that hit first‐silicon functional goals. Optimise multi‐lane protocols for bandwidth scaling, skew management and power efficiency ; integrate error monitoring More ❯