Senior / Staff Digital Design Engineer
South East London, England, United Kingdom
Flux Computing
and implement high‐throughput digital pipelines (multi‐GSPS input rate, continuous streaming data paths, deep pipelining and hand‐shaking) in advanced CMOS nodes. Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‐up real‐time demos, exercise high‐speed transceivers, and feed learnings back into the ASIC. Model algorithms and validate concepts in MATLAB … GbE or similar). Expertise with industry‐standard EDA flows: RTL synthesis, CDC/RDC, STA, power‐intent (UPF/CPF), lint, and gate‐level simulation. Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab. Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed‐point analysis and test‐vector … of coherent optical links or photonic‐electronic co‐design. Familiarity with AI/ML workloads, systolic arrays or tensor‐processing architectures. Contributions to open‐source RTL, verification frameworks or FPGA boards. Compensation & Benefits Competitive salary ranging from £135k+, depending on experience. Stock options in a rapidly growing AI company. Based in our new 5,000 sq. ft. office in More ❯
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