2 of 2 FPGA Design Jobs in the North East

Contract FPGA Engineer – Defence Sector | Outside IR35 | £60–£70/hr Location: Edinburgh (Hybrid Working) Rate: £60–£70 per hour Contract Type: Outside IR35 Clearance: SC Cleared or Eligible Sector: Defence & Mission-Critical Systems 🧠 The Opportunity We’re working with a leading service provider in the defence sector on a new Statement of Work (SOW) and are looking for … an experienced FPGA Engineer to join their Edinburgh-based team. This is a fantastic opportunity to contribute to cutting-edge defence systems in a role that offers both technical challenge and flexibility. 🔍 What You’ll Be Doing You’ll play a key role in the design and development of complex FPGA-based systems, including: Developing concepts … for advanced digital functions and systems Designing and analysing FPGA architectures Creating documentation for design reviews Planning and developing test strategies Integrating and verifying designs Ensuring all firmware development aligns with industry and internal standards ✅ What We’re Looking For Proven experience in FPGA design (VHDL/Verilog) Strong background in digital electronics and More ❯

Senior/Principal FPGA Engineer Edinburgh (Hybrid, 2 days from home) circa £88 per hour + overtime Contract position Virtual interview Mon–Fri Certain Advantage is collaborating with a key client to recruit Senior/Principal FPGA Engineers who will be responsible for the design and development of FPGA designs using VHDL and verifying designs … using VHDL or System Verilog. What will you be doing? Creating innovative and robust VHDL-based designs Documenting and recording deliverables Verifying FPGA designs Ensuring configuration management/keeping designs under revision control Providing progress reports A couple of things you should know: At least 5 years’ experience of developing FPGA using VHDL or Verilog Experienced with Mentor … Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. Independent verification using VHDL Experience of FPGA requirements capture and requirements More ❯