As Control Systems Engineer, you'll own the full lifecycle of automation control and safety systems - from concept through commissioning. Working alongside production, maintenance, and engineering, you'll ensure critical assets run safely, efficiently, and reliably. Client Details Our client is a specialist manufacturer with multiple sites across the UK and a strong international footprint. They operate in a … niche industrial sector with continual investment in automation and process innovation. Their Lydney facility is undergoing a period of expansion, with major upgrades to safety systems, controls, and production technology - creating an exciting opportunity for a skilled engineer to make an immediate impact. Description Key Responsibilities Design, program, and commission PLC and motion control systems (Siemens TIA/Step7 … Mitsubishi, Beckhoff). Develop and integrate functionalsafety systems (light curtains, scanners, safety PLCs, interlocks). Create and maintain documentation - FDS/URS, risk assessments, validation plans, and AutoCAD drawings. Deliver SCADA/HMI systems with data acquisition, alarm, and diagnostic capability. Lead automation projects from concept through to handover. Troubleshoot chronic faults, drive root-cause fixes More ❯
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functionalsafety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functionalsafety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functionalsafety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯
