Mitsubishi, Rockwell, Schneider) Experience with instrumentation and control loops in a process industry environment Self motivated with the ability to manage and prioritise a demanding workload Demonstrate a site safety culture, cyber security and process safety A formal electrical/Instrumentation qualification: National Certificate (ONC) or similar The ability to read and understand technical documents such as loop … diagrams and electrical drawing You will also benefit from having: A recognised electrical/Instrumentation craft or technician apprenticeship Experience working with FunctionalSafety and/or in a regulatory environment Experience of the Water Industry or other process environment Experience with Operational Technology data communications We embrace a flexible working model, where our hybrid setup typically requires More ❯
Bradford, south west england, united kingdom Hybrid / WFH Options
Yorkshire Water
Mitsubishi, Rockwell, Schneider) Experience with instrumentation and control loops in a process industry environment Self motivated with the ability to manage and prioritise a demanding workload Demonstrate a site safety culture, cyber security and process safety A formal electrical/Instrumentation qualification: National Certificate (ONC) or similar The ability to read and understand technical documents such as loop … diagrams and electrical drawing You will also benefit from having: A recognised electrical/Instrumentation craft or technician apprenticeship Experience working with FunctionalSafety and/or in a regulatory environment Experience of the Water Industry or other process environment Experience with Operational Technology data communications We embrace a flexible working model, where our hybrid setup typically requires More ❯
Somerset, South West, United Kingdom Hybrid / WFH Options
Outsource UK lTD
or similar) Familiarity with Modbus communication, PID loops, P&I diagrams, and electrical schematics Understanding of compliance standards such as LVD (EN/UL61010, EN60204), EMC (EN61326-1), and FunctionalSafety (EN61508) Strong communication and influencing abilities Proactive problem-solving and collaboration mindset Highly organised and able to manage changing priorities Passion for innovation and learning best practices More ❯
Kenn, Clevedon, Avon, England, United Kingdom Hybrid / WFH Options
Outsource
or similar) Familiarity with Modbus communication, PID loops, P&I diagrams, and electrical schematics Understanding of compliance standards such as LVD (EN/UL61010, EN60204), EMC (EN61326-1), and FunctionalSafety (EN61508) Strong communication and influencing abilities Proactive problem-solving and collaboration mindset Highly organised and able to manage changing priorities Passion for innovation and learning best practices More ❯
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functionalsafety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functionalsafety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯
a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to … Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functionalsafety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. Excellent communication skills and a methodical, detail-focused approach. Apply to learn more More ❯