16 of 16 Git Jobs in County Antrim

containers Experience with monitoring systems, e.g. Zabbix, Nagios etc. Experience of JIRA and Confluence Nginx or web server technologies Gluster or storage technologies Git and version control Elasticsearch technologies - especially Kibana Experience with Apache Kafka and Druid At Partnerize, we recognize it is unrealistic for a candidate to fulfil ...

Python 3 and FastAPI Knowledge of Java, maven and the Spring Boot, GraphQL API Experience with PostgreSQL, TimescaleDB Knowledge of Docker environment Knowledge of Git, Linux Knowledge of AWS If this sounds like you then we'd love to hear from you. Are you ready for a career with ...

other staff Ensure security and compliance requirements are met Who You Are 6+ years of relevant work experience Strong experience with Kubernetes, Docker, Git, Linux, Bash, Terraform is a must Confidence working with monitoring and alerting systems such as Prometheus Experience in deployment of complex software solutions ...

accelerators to speed up delivery and improve consistency. Define ALM (Application Lifecycle Management) processes for Power Platform using tools such as Azure DevOps/Git, solution layering, and pipelines. Support the creation of governance documentation, standards, and design patterns across the platform. 4. Integration & Data Architecture Design integrations between ...

Have Experience in low-latency or multi–data center environments Exposure to cloud networking (AWS, Azure, or GCP) Experience with NetOps tools and practices (Git, CI/CD, Terraform, monitoring platforms) If this is an opportunity you'd like to explore, please get in touch: Email: james.good@radleyjames.com Mobile ...

weeks) The second step includes a selection of more advanced courses to get you up to speed. Learn the Command Line (1.5 weeks) Learn Git & GitHub (1.5 weeks) Learn JavaScript (1.5 weeks) Learn Python 3 (1.5 weeks) JavaScript forms the foundation of almost everything you see on the Internet ...

required and relevant for many entry level programming roles and help you get a step ahead. Learn the Command Line (*1.5 weeks) Learn Git & GitHub (*1.5 weeks) Learn JavaScript (*1.5 weeks) Learn Python 3 (*1.5 weeks) JavaScript forms the foundation of almost everything you see on the Internet. Therefore ...

choice. Excellent understanding of software architecture, performance tuning, and scalable code patterns. Strong collaboration skills and experience working within distributed, asynchronous teams. Comfortable using Git, CI/CD systems, and participating in open-source governance workflows. Compensation & Legal Hourly contractor via Mercor. Payments processed weekly through Stripe Connect. Application ...

Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient with Git , CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC , Vivado , Vitis Whats on Offer Long-term programme with high technical impact Opportunity ...

Data Handling – Real-time data acquisition, Historian integration, data replication, and logging Performance Tuning & Monitoring – Query optimization, indexing, database health monitoring Version control with Git, SVN, or equivalent ...

Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC, SoC, or IP verification environments Desirable Experience with Vivado/Vitis or adaptive SoC flows Embedded processor co-simulation ...

drive constrained-random and coverage-driven verification Automate regressions using Python scripting Work within CI/CD environments and version control using Git Support ASIC/SoC/FPGA verification flows Essential Skills & Experience Strong experience as a Verification Engineer/ASIC Verification Engineer Proven UVM and class-based … verification expertise Solid background in DSP verification (FFT, FIR, signal processing) Python for automation and regression Experience with SoC/ASIC/FPGA environments Git version control Desirable MATLAB experience Exposure to Vivado/Vitis or adaptive SoC flows Contract role | Market rate | Remote working If youre a senior ...

focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting … flow: synthesis, P&R, timing closure High-speed digital interfaces: 100GbE/PCIe Gen5/AXI Vivado/Vitis toolchain expertise Python/Tcl, Git, CI/CD experience Details Contract: 6 months + extension Location: Remote (UK) Start: ASAP Rate: Market rate If you are a Senior ...

focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … flow: synthesis, P&R, timing closure High-speed digital interfaces: 100GbE/PCIe Gen5/AXI Vivado/Vitis toolchain expertise Python/Tcl, Git, CI/CD experience Details Contract: 6 months + extension Location: Remote (UK) Start: ASAP Rate: Market rate If you are a Senior ...

focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … flow: synthesis, P&R, timing closure High-speed digital interfaces: 100GbE/PCIe Gen5/AXI Vivado/Vitis toolchain expertise Python/Tcl, Git, CI/CD experience Details Contract: 6 months + extension Location: Remote (UK) Start: ASAP Rate: Market rate If you are a Senior ...

focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … synthesis, P&R, timing closure High-speed digital interfaces: 100GbE/xkybehq PCIe Gen5/AXI Vivado/Vitis toolchain expertise Python/Tcl, Git, CI/CD experience Details Contract: 6 months extension Location: Remote (UK) Start: ASAP Rate: Market rate If you are a Senior IP Design ...