4 of 4 Hardware Design Engineer Jobs in London

Join to apply for the Senior FPGA Design Engineer/Hardware Engineer role at Maven Securities Join to apply for the Senior FPGA Design Engineer/Hardware Engineer role at Maven Securities Get AI-powered advice on this job and more exclusive features. ABOUT THE COMPANY: Maven is a market-leading proprietary … leverage groundbreaking execution and pricing technologies to elevate and improve how financial markets operate. Overview: Where technology meets trading, the Maven FPGA team is pushing the bleeding edge of hardware and proprietary designs to maintain and gain advantage in an increasingly competitive environment. With operations in London, New York, Hong Kong and Chicago, we build technology in support of … other DSP flow experience for FPGA Comfortable attacking new and unfamiliar problems Interest in trading Things we would like to see but are not essential: Python, TCL Low latency design ASIC Network and packet processing Financial market data Trading systems Software development What We Offer Competitive compensation Group Pension plan Annual discretionary bonus Fully catered breakfast, lunch and snacks. More ❯

JOB AD: Job Title:Hardware Design EngineerPosition:Full time/PermanentLocation:London/Hybrid Salary Range:40K - 50K DOE Client Information: We are looking for a talented and motivated Hardware Design Engineer to join our UK GPU team. Candidates with GPU architecture or design experience are highly preferred. Responsibilities: Spec writingDevelop and implement RTL … designs using Verilog/SystemVerilog/VHDL for complex digital blocks. Collaborate closely with architecture, verification, and physical design teams throughout the development cycle. Perform design synthesis, linting etc.Participate in design reviews and contribute to design optimization and improvements. Support post-silicon bring-up and debug if needed. Requirements: Bachelor's or Master's degree in … Electrical Engineering, Computer Engineering, or a related field. 3 to 5 years of experience in frontend RTL design. Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL.Familiar with ASIC design flow and tools (e.g., lint, synthesis, simulation). More ❯

Job Title: Hardware Design and Verification Engineer Position: Junior - Mid level Engineers Type: Contract or Permanent Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information: We are building a revolutionary RISC-V-based GPU and AI platform, and we're hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. … If you thrive on innovation and want to work on cutting-edge vector processing and neural compute technologies, this is your opportunity. Design Responsibilities: Architect and implement RTL for critical blocks within our RISC-V vector core GPU Design high-performance, power-efficient compute units for graphics and AI workloads Optimize microarchitecture to meet performance, power, and area … PPA) targets Work collaboratively with verification teams to ensure correctness and efficiency Participate in design reviews and contribute to technical decision-making Document technical specifications and development progress Contribute to bring-up, synthesis, and physical-aware design flows Verification Responsibilities: Develop UVM/SystemVerilog testbenches and functional verification plans Implement directed and constrained-random tests for robust coverage More ❯

leverage groundbreaking execution and pricing technologies to elevate and improve how financial markets operate. Overview: Where technology meets trading, the Maven FPGA team is pushing the bleeding edge of hardware and proprietary designs to maintain and gain advantage in an increasingly competitive environment. With operations in London, New York, Hong Kong and Chicago, we build technology in support of … other DSP flow experience for FPGA Comfortable attacking new and unfamiliar problems Interest in trading Things we would like to see but are not essential: Python, TCL Low latency design ASIC Network and packet processing Trading systems WHAT WE OFFER Competitive compensation Annual discretionary bonus Fully catered breakfast, lunch and snacks. 25 days annual leave Informal dress code Private More ❯