3 of 3 IP Design Engineer Jobs in the UK excluding London

Senior IP Design Engineer

Hiring Organisation
Infoplus Technologies UK Ltd
Location
Belfast, County Antrim, Northern Ireland, United Kingdom
Employment Type
Contract
Contract Rate
From £300 to £450 per day
Description: Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe … Gen5, AMBA/AXI Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure Vivado/Vitis expertise Python/Tcl scripting Git & CI/CD experience ...

Senior IP Design Engineer

Hiring Organisation
Infoplus Technologies UK Ltd
Location
Finaghy, Belfast, UK
Description: Check below to see if you have what is needed for this opportunity, and if so, make an application asap. Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver … designs meeting timing and integration requirements. Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding of FPGA/Adaptive xkybehq SoC design flow including P&R and timing closureVivado/Vitis expertisePython/Tcl scriptingGit & CI/CD experience ...

Senior IP Design Engineer

Hiring Organisation
Infoplus Technologies UK Ltd
Location
Newtownabbey, Co. Antrim, UK
Description: Is this the role you are looking for If so read on for more details, and make sure to apply today. Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK Hybrid Job details:Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. … designs meeting timing and integration requirements. Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding of FPGA/Adaptive xkybehq SoC design flow including P&R and timing closureVivado/Vitis expertisePython/Tcl scriptingGit & CI/CD experience ...