all aspects of Physical construction and Integration. Knowledge in Physical Design Verification methodology LVS/DRC. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). Great teammate, self-learning skills, and ability to work autonomously. , where each person is unique, but together we bring our talents to More ❯
LVS, ANTENNA, ERC). Solid understanding of synthesis, floorplanning, placement, CTS, routing, and STA concepts. Experience with physical design tools such as: Synthesis tools: Synopsys DC, Cadence RC Formal verification tools: Formality, Formalpro Physical verification tools: Mentor Calibre, Synopsys IC Validator Demonstrated ability to solve problems independently and as part More ❯
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips … phase to catch bugs early in the development cycle. Working independently with sales, R&D, and other field AE teams to ensure customer and Synopsys goals are met. Creating and examining functional coverage and writing SystemVerilog assertions. Debugging RTL and gate-level simulation failures and firmware. Tracking bugs using software … products. Identifying and rectifying bugs early in the development cycle, reducing costs and time to market. Collaborating across teams to drive innovation and achieve Synopsys' goals. Enhancing customer satisfaction through successful consulting and support. Contributing to the development of cutting-edge technologies in the semiconductor industry. Potentially growing into a More ❯
