Lead Design Engineer
Edinburgh, United Kingdom
Cadence Design Systems
verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Experience with FPGA emulation, design tools, and verification desirable Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of More ❯
Employment Type: Permanent
Salary: GBP Annual
Posted: