1 to 25 of 27 Synopsys Jobs in the UK excluding London

CI/CD.) Willing to learn new development languages, tools, frameworks and techniques. "Nice To Have" Skills and Experience: Experience in hardware functional verification (Verilog, VHDL, SystemVerilog, systemC. Using Synopsys, Cadence or Siemens tools). Knowledge of more programming languages like C, Go, JavaScript, Ruby, Perl, Tcl. Experience with Docker (images creation, testing and distribution) and cloud-computing providers (AWS More ❯

UVM (Universal Verification Methodology) and coverage-driven verification Skilled in analyzing waveforms, simulation outputs, and debugging complex digital behaviors Synthesis, Implementation & File Generation Proficient in synthesis and implementation using: Synopsys Design Compiler Cadence Genus Xilinx Vivado Intel Quartus Prime Experienced in generating and managing key implementation deliverables: .lib files for timing and cell characterization .lef files for physical abstraction of … Test Pattern Generation (ATPG) and analyzing test coverage reports Understanding of DFT constraints and impact on design timing and area Tools & Workflow Automation Experienced with industry-standard EDA tools : Synopsys, Cadence, Siemens/Mentor, Xilinx, Intel Proficient in version control systems such as Git for collaborative development Skilled in scripting and workflow automation using Python , TCL , Make , and Shell scripting More ❯

V ISA is a plus, not a mustUnderstanding of pipelining, memory hierarchies, or parallel compute conceptsInterest in learning physical design fundamentals (timing, DFT, floorplanning)Experience using EDA tools (e.g., Synopsys, Cadence, or similar) during academic or internship projects Scripting knowledge in Python, TCL, or equivalent languagesBS or MS in Electrical Engineering, Computer Engineering, or a related discipline Verification Requirements0 More ❯

tools desired. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools. Experience in MBIST implementation and verification will be a strong plus. Good understanding of STA concepts having handled DFT … timing closure before would be a plus. Experience in Spyglass based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus. Prior experience in working with Version control systems like perforce, git etc would be critical. Understanding of Logic Equivalence, CDC, Lint, UPF/ More ❯

of the DFT structures to meet the project's testability requirements. DFT Expertise: Serve as an expert in DFT tools and techniques, demonstrating advanced skills in tools from Mentor, Synopsys, or Cadence. Complex Problem Solving: Address and resolve complex issues related to DFT, ATPG, timing closure, and ATE chip bring-up, providing solutions to challenges across multiple projects. Leadership & Mentorship … Project Management skills. Desirable: A project management qualification. Additional experience in high-level design teams, especially in DFT architecture. Skills & Experience: Essential: Extensive experience with DFT tools (e.g., Mentor, Synopsys, Cadence) and techniques including: IJTAG/Scan/MBIST/BSD/LBIST/Boundary Scan insertion. ATPG/TC improvements and pattern generation. Pattern simulation (Zdel/SDF) and More ❯

and methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

environments. Core DFT Competencies : Experience with hierarchical scan, memory BIST, JTAG/IJTAG, at-speed testing, ATPG, fault simulation, and silicon debug. Tools Experience : Familiarity with Siemens, Cadence, and Synopsys DFT tools. Problem-Solving Skills : Exceptional troubleshooting and debugging abilities. Communication Skills : Fluent in English, with a collaborative approach to complex technical discussions. Ready to Shape the Future? If you More ❯

SoCs. Partner with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence More ❯

physical verification checks (e.g., DRC, LVS, ANTENNA, ERC). Solid understanding of synthesis, floorplanning, placement, CTS, routing, and STA concepts. Experience with physical design tools such as: PnR tools: Synopsys ICC, Cadence EDI, Mentor Olympus Synthesis tools: Synopsys DC, Cadence RC Formal verification tools: Formality, Formalpro Physical verification tools: Mentor Calibre, Synopsys IC Validator Demonstrated ability to solve problems independently More ❯

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through … The Netherlands What You’ll Be Doing: Providing our customers with technical and engineering expertise in their ASIC design hardware verification process, using our HAV Platforms and Solutions. Pitching Synopsys Emulation and Prototyping HAV solutions to potential customers. Analyzing customers' verification methodologies and targets, and planning platform and Testbench solutions. Driving and executing Synopsys HAV product evaluations on customers' designs. … on account strategies and business growth opportunities. The Impact You Will Have: Enhancing the efficiency and effectiveness of our customers' hardware verification processes. Contributing to the successful deployment of Synopsys HAV solutions in complex SoC designs. Driving customer satisfaction through expert technical support and problem-solving. Influencing the development of future Synopsys HAV products through feedback and collaboration with R More ❯

Work in a team environment developing high-performance instruction accurate models of Arm CPUs and System Level IP models Develop Virtual Platforms for testing Integrate models and platforms from Synopsys partners Contribute to the continuous improvement of Synopsys modelling methodologies. Configure and bring up complex software stacks and drivers on the simulated hardware Work closely with other development teams, 3rd … party suppliers, support engineers and customers to identify, implement and deliver solutions Interact with Synopsys development teams working on other modelling technologies, advanced architectures, hardware design, software design, and validation Based in central Edinburgh with some working from home allowed. Key Requirements/Qualifications: Good programming skills in C and C++ Scripting Languages, preferably Python Excellent communication and problem-solving … and transaction-level modelling knowledge would be beneficial but not essential, as would familiarity with high performance modeling (Dynamic Binary Translation (DBT), Just In Time (JIT) code morphing) At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs More ❯

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through … verifying functionality in the design phase to catch bugs early in the development cycle. Working independently with sales, R&D, and other field AE teams to ensure customer and Synopsys goals are met. Creating and examining functional coverage and writing SystemVerilog assertions. Debugging RTL and gate-level simulation failures and firmware. Tracking bugs using software tools such as Jira and … to reliable and high-quality products. Identifying and rectifying bugs early in the development cycle, reducing costs and time to market. Collaborating across teams to drive innovation and achieve Synopsys' goals. Enhancing customer satisfaction through successful consulting and support. Contributing to the development of cutting-edge technologies in the semiconductor industry. Potentially growing into a leadership role, shaping the future More ❯

Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. (PLUS) Proven experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other More ❯

VHDL design and verification Strong technical reporting skills Ability to manage complex products Beneficial experience includes familiarity with tools like Azure DevOps, Git, IBM DOORS, Siemens QuestaSim/ModelSim, Synopsys Synplify Pro, and knowledge of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254, as well as languages like VHDL, SystemVerilog, TCL, Python. The package includes a More ❯

verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Experience with FPGA emulation, design tools, and verification desirable Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of More ❯

Overview: Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to More ❯

within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or Mentor platforms). Solid understanding of RTL design , STA , and silicon test methodologies . A proactive, solution-oriented mindset and excellent collaboration skills. For more information please contact More ❯

Strong understanding of Place & Route flow. Preferred Qualifications Deep understanding of Physical construction and Integration. Knowledge of Physical Design Verification (LVS/DRC). Familiarity with EDA tools like Synopsys, Cadence. Good teamwork, self-learning skills, and ability to work independently. Learn More Cisco Silicon One Overview Fortune Article on Cisco Silicon One Calcalist Article Cisco Silicon One on YouTube More ❯

Qualifications Deep understanding of all aspects of Physical construction and Integration. Knowledge of Physical Design Verification methodologies (LVS/DRC). Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). Great teammate, self-learning skills, and ability to work autonomously. Learn More About Us Here: Cisco Silicon One Overview Fortune Article on Cisco Silicon One Calcalist Article More ❯

experience in physical design. You have an excellent understanding of digital physical implementation and advanced CMOS technologies. You are a proficient user of EDA tools (Cadence and/or Synopsys). You understand advanced semiconductor fabrication processes and devices. You are detail-oriented but are also comfortable in critical thinking and making decisions to navigate the changing R&D demands. More ❯

Advantageous Qualifications Deep understanding of all aspects of Physical construction and Integration. Knowledge in Physical Design Verification methodology LVS/DRC. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). Great teammate, self-learning skills, and ability to work autonomously. , where each person is unique, but together we bring our talents to work as a team and More ❯

Fixed-term: The funds for this post are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK More ❯

Fixed-term: The funds for this post are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK More ❯

and package-level; preferred to have GaN experiences as well. A good understanding of statistical analysis and design of experiments Knowledge of semiconductor TCAD tools for device simulation, i.e. Synopsys Sentaurus, Silvaco Victory Background in electronics engineering for system understanding in the field of power electronics. Excellent problem-solving skills – able to identify problems and/or opportunities for improvement More ❯

and package-level; preferred to have GaN experiences as well. A good understanding of statistical analysis and design of experiments Knowledge of semiconductor TCAD tools for device simulation, i.e. Synopsys Sentaurus, Silvaco Victory Background in electronics engineering for system understanding in the field of power electronics. Excellent problem-solving skills – able to identify problems and/or opportunities for improvement More ❯