of RTL synthesis, performance, and power analysis. In-depth understanding of digital design concepts and problem-solving capabilities. Proficient in HDL coding (VHDL, Verilog, SystemVerilog). System design knowledge, including clock domain management, reset schemes, and power management. Experience with SoC level verification (HW/SW co-verification, multi-mode More ❯
Reading, England, United Kingdom Hybrid / WFH Options
JR United Kingdom
help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯
trading and engineering teams to ensure robust, reliable systems Key Requirements: Strong experience in functional verification, including coverage models, reusable testbenches, and randomized testing (SystemVerilog, UVM, or cocotb) Proficient in Python and C++ in a Linux environment Comfortable with CI/CD workflows (Jenkins, GitLab CI, Bamboo, etc.) Understanding of More ❯
ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone More ❯
metrics to track and report progress. Troubleshoot, debug, and resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures More ❯
range of projects that will both challenge and develop your technical and verification skills. You will have a good understanding of different methodologies, particularly SystemVerilog, UVM and MS-UCM. You will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy and More ❯
metrics to track and report progress. Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests. Requirements: Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies. A solid understanding of mixed hardware/software verification approaches. Experience with RISC-V architectures More ❯
Aion Silicon is looking for an experienced Verification Engineers to join our office in Theale/Bristol. In this hands-on technical role, you will contribute to a variety of SoC, subsystem, and IP development projects, taking responsibility for the More ❯
Principal Application Engineer (Palladium Emulation) Join or sign in to find your next job Join to apply for the Principal Application Engineer (Palladium Emulation) role at Cadence Principal Application Engineer (Palladium Emulation) 1 week ago Be among the first 25 More ❯
verification and emulation. You possess a deep understanding of ASIC/SoC design and verification processes, and you are proficient in HVL languages like SystemVerilog, C/C++, Unix/Linux, and scripting languages. You have hands-on experience with hardware emulators or prototyping platforms, and you are knowledgeable about …/SoC design and/or verification processes. Direct experience with hardware emulators or prototyping platforms is highly preferred. Proficiency in HVL languages like SystemVerilog, C/C++, Unix/Linux development environment, and scripting languages. Knowledge of key protocols such as Ethernet, PCIe, AMBA, UART, and DDR. Strong HW More ❯
Newbury, Berkshire, United Kingdom Hybrid / WFH Options
Siemens AG
About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯
will participate in the following activities: Digital design using RTL coding, block and top-level verification, digital constraints, synthesis, ATPG, STA, etc. Expertise in SystemVerilog and RTL design and verification Coding skills in tcl/perl/Python and Verilog/SystemVerilog RTL Experience in maintaining design processes Added Value … Leadership in process and quality improvements Requirements: Bachelor's/Master's in Electronics/Computing Fluency in English (written and spoken) Knowledge of SystemVerilog, digital circuit design (state machines, control logic, filters, memory interfaces), digital verification (randomized testing, code coverage, verification), UVM (a plus), logic synthesis, DFT, ATPG, STA More ❯
a 6-month fixed contract with a view to go into a permanent position. The Lead Verification Engineer will have expertise in UVM and SystemVerilog to support the development and verification of complex ASIC designs. Responsibilities Develop and implement verification environments using UVM methodology Create verification plans and test cases … methodology improvements and best practices Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science 10+ years industry experience Proficiency in SystemVerilog and UVM for ASIC verification Solid understanding of digital design fundamentals Experience with industry-standard simulation and verification tools Strong problem-solving skills and attention More ❯
Social network you want to login/join with: Application Specific Integrated Circuit Design Engineer, reading col-narrow-left Client: IC Resources Location: reading, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 3 More ❯
Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯
Maidenhead, Royal Borough of Windsor and Maidenhead, Berkshire, United Kingdom
Platform Recruitment
Senior FPGA Engineer | £80-100k | Slough | Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯
strategies, you thrive on ensuring that designs comply with protocol standards and system requirements. You are experienced in creating and examining functional coverage, writing SystemVerilog assertions, and debugging RTL and gate-level simulation failures. Your background in firmware debugging and bug tracking using software tools like Jira sets you apart. … with sales, R&D, and other field AE teams to ensure customer and Synopsys goals are met. Creating and examining functional coverage and writing SystemVerilog assertions. Debugging RTL and gate-level simulation failures and firmware. Tracking bugs using software tools such as Jira and performing code coverage analysis. The Impact … the future of the verification team. What You'll Need: In-depth understanding of verification flows, test plans, and strategies. Expertise in constrained-random SystemVerilog testbenches using UVM or VMM. Experience in creating and examining functional coverage and writing SystemVerilog assertions. Skills in debugging RTL and gate-level simulation failures More ❯
Reading, England, United Kingdom Hybrid / WFH Options
JR United Kingdom
Social network you want to login/join with: At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking an experienced RTL Engineer to join our client's team. Our mission is to be More ❯