2 of 2 SystemVerilog Jobs in Cambridge

software and infrastructure teams to optimise full-stack performance. Requirements: 7+ years FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Bonus ...

test) Strong background in Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k–£120k + equity ...