7 of 7 SystemVerilog Jobs in Cambridge

strategies, and Agile development practices. Work closely with software and ML engineers to deliver efficient, scalable inference applications. Were looking for someone with: 5+ years experience writing well-documented SystemVerilog/Verilog/VHDL. Strong FPGA toolchain knowledge (Quartus, Vivado, or equivalent). Experience in debugging, bring-up, and timing optimisation of FPGA designs. Exposure to C/C++ or More ❯

be the right fit. FPGA Engineer requirements: Minimum 3+ years commercial FPGA Engineering (Implementation, simulation, verification and test) Excellent academic background with degree from a top university Coding in SystemVerilog or VHDL FPGA external interface designs (e.g. PCIe, Aurora, Ethernet, SPI etc.) Some exposure to digital signal processing Proactive, collaborative mindset with ownership of projects This is a rare chance More ❯

Required Skills and Experience: BSc, MSc or PhD degree qualification in Electronics/Computer Engineering or equivalent Ability to understand and use Hardware Description Languages (HDLs) such as Verilog, SystemVerilog or VHDL Strong interest in and understanding of CPU architectures and SoC design principles Experience in using RTL simulation tools for debugging purposes Ability to learn and communicate IP product More ❯

D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. … in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such More ❯

D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. … in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such More ❯

Microarchitect & RTL Design Engineer Cambridge,/Bristol England, United Kingdom We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified More ❯

Microarchitect & RTL Design Engineer Cambridge,/Bristol England, United Kingdom We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified More ❯