1 to 25 of 58 SystemVerilog Jobs in Cambridgeshire

DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design tools (P&R). Proficiency in SystemVerilog, C, SystemC, C++, Python, Perl, or TCL. Knowledge of place and route methodologies. Strong communication skills, both written and spoken, in English. Who we are More ❯

Exposure to verification tools such as UVM or formal verification methodologies. Exposure to ASIC, FPGA, and physical design tools (P&R). Proficiency in SystemVerilog, C, SystemC, C++, Python, or TCL. Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its More ❯

will show your: Good degree in electronics or another technical subject from a top university Extensive experience developing complex and well-structured RTL in SystemVerilog, Verilog or VHDL, with particular attention to design approach and performance constraints And as a skilled FPGA Design Engineer you will also have, as your More ❯

who can additionally demonstrate the following will be strongly preferred: Knowledge of development for embedded platforms; Interest or experience with FPGAs, VHDL, Verilog, or SystemVerilog; Interest in the AR/VR field; Interest in high-performance parallel computing. What do we offer? Employee share options scheme (the earlier you join More ❯

might also have experience of one or more of the following: Build systems (e.g. Bazel, Nextflow, FuseSoC) Hardware EDA tools (eg. simulation, linting, synthesis) Systemverilog, C/C++, Simulator DPI/VPI Containerization (eg. Docker) Distributed Compute, Orchestration Jenkins Automation Software templating, rendering Data Engineering/Data Science/Machine More ❯

The ideal FPGA Engineer candidate will have: Experience in FPGA Design and Development DSP experience within an FPGA environment Proficiency in VHDL, Verilog, and SystemVerilog Software development skills in C, C++, or Python Knowledge of Sonar, Radar, or other sensor systems If you are considering a new challenge, please apply More ❯

through to the implementation and verification of these systems. Key Requirements Extensive experience working across the entire FPGA design cycle Strong command of VHDL, SystemVerilog and Xilinx design tools Solid understanding of the design of high-speed digital circuits for real-time systems and experience implementing signal processing algorithms with More ❯

through to the implementation and verification of these systems. Key Requirements Extensive experience working across the entire FPGA design cycle Strong command of VHDL, SystemVerilog and Xilinx design tools Solid understanding of the design of high-speed digital circuits for real-time systems and experience implementing signal processing algorithms with More ❯

cutting-edge AI-capable FPGAs and help define the team's workflows. The ideal candidate will have experience with: Full FPGA development lifecycle Verilog, SystemVerilog, and VHDL C, C++, or Python Tools such as Quartus and Vivado RTL design optimization Linux development environments If you are interested in AI technology More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

help build low-latency/high-throughput applications. What skills and experience are required: FPGA design, development, and testing experience Previous experience in using SystemVerilog, VHDL, and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

signal processing components, leading system design, architecture, implementation, and verification. Key Requirements Extensive experience across the entire FPGA design cycle Strong command of VHDL, SystemVerilog, and Xilinx design tools Solid understanding of high-speed digital circuit design for real-time systems and experience implementing signal processing algorithms with high-speed More ❯

also guide and support other team members. Required Skills and Experience: Experience in RTL design for complex SoC development using Verilog and/or SystemVerilog Knowledge in static design checks, synthesis and timing analysis, power management techniques, and power and clock domain crossing Understanding of computer architecture and systems, with More ❯

Being a positive team influence. Optional or desired experience includes: Build systems (e.g., Bazel, Nextflow, FuseSoC). Hardware EDA tools (simulation, linting, synthesis). SystemVerilog, C/C++, Simulator DPI/VPI. Containerization (e.g., Docker). Distributed computing and orchestration. Jenkins automation. Software templating and rendering. Data engineering, data science More ❯

or an excitement to learn, one or more of the following: Build systems (e.g. Bazel, Nextflow, FuseSoC) Hardware EDA tools (eg. simulation, linting, synthesis) Systemverilog, C/C++, Simulator DPI/VPI Containerization (eg. Docker) Distributed Compute, Orchestration Jenkins Automation Software templating, rendering Data Engineering/Data Science/Machine More ❯

EDA tools and able to script and automate workflow when needed. Excellent oral and written communications skills Preferred Qualifications Expert in HVL such as SystemVerilog, UVM Strong working knowledge of digital design and SoC architecture Experience in creating complex test scenarios and reproducing real world failures. Scripting in Perl, TCL More ❯

the implementation team to optimize those designs. Required Skills and Experience: Experience of RTL design for complex SoC development using Verilog and/or SystemVerilog Experience or knowledge in the following areas: Static design checks, Synthesis and timing analysis, Power management techniques, Power and Clock domain crossing An understanding of More ❯

CSI/DSI Experience of interconnect standards ACE, AXI, AHB, and APB Ability to form requirements and specify architectural features Expert-level Verilog/SystemVerilog for design and verification Familiarity with scripting languages (Bash, Python, Tcl, etc) The following would also be useful: Experience of Cadence simulation tool flow Experience More ❯

with the implementation team to optimize designs. Required Skills and Experience: Experience in RTL design for complex SoC development using Verilog and/or SystemVerilog Knowledge in static design checks, synthesis, timing analysis, power management techniques, and power and clock domain crossing An understanding of computer architecture and systems, with More ❯

of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively More ❯

Description: Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys. Be fluent in SystemVerilog, Verilog or VHDL and familiar with LINT, simulation and synthesis. Familiarity with architectures for secure systems design, e.g., cryptographic encoders/decoders or tagged processor More ❯

of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯

Responsibilities: Develop digital designs for custom IC integration Design and validate new silicon designs Experience required: ASIC or FPGA Design experience Strong Verilog and SystemVerilog skills Python experience Knowledge of CPU architecture is a plus You will be part of a stimulating and exciting work environment, involved throughout the entire More ❯