9 of 9 SystemVerilog Jobs in East Anglia

implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯

language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯

GPU systems. Prior working knowledge of crafting scalable memory systems, cache coherence, and address translation. Must have written a whole lot of HDL (Verilog, SystemVerilog, VHDL) code at some point in your career. Strong programming and coding skills is essential. Demonstrative knowledge of GPU systems and prior working experience in More ❯

FPGA Engineers Rates up to £100 Per hour - 12 month contract - Inside IR35 4 days on site - hybrid SC Cleared or SC Clearable We are seeking several Firmware/FPGA Engineers (at various levels of experience) to join our clients More ❯

are robust, high-performing, and built to scale. What you will be doing: • Creating and executing thorough verification plans for complex hardware designs • Developing SystemVerilog/UVM testbenches for functional verification • Running directed and constrained-random tests • Maintaining regression suites to validate design quality • Supporting system-level performance validation • Debugging … design engineers • Using formal verification techniques when appropriate Requirements: • 5+ years of hands-on experience in hardware verification (preferably in SoCs) • Strong skills in SystemVerilog and UVM • Experience with modern verification tools (ABV, CDV, etc.) • Bonus: Experience with GPU, vector processors, or AI accelerators • Bonus: Familiarity with RISC-V architecture More ❯

What You’ll Do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs … commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already More ❯

Design Engineer is sought to join a dynamic team. The ideal candidate will have a strong background in RTL Design and be proficient in SystemVerilog and Verilog. This position offers the opportunity to work on cutting-edge projects and contribute to the development of innovative solutions in the field of … working with and huge growth plans. Responsibilities Collaborates with cross-functional teams to define and implement ASIC architectures Designs and develops RTL code using SystemVerilog and Verilog Conducts design verification and ensures compliance with specifications Participates in the integration and testing of ASICs Contributes to the improvement of design methodologies … Bachelor's or Master's degree in Electrical Engineering or related field Demonstrates a solid understanding of ASIC design principles and methodologies Proficient in SystemVerilog, Verilog, and RTL Design Possesses familiarity with security-related applications and protocols, which is a plus Exhibits strong problem-solving skills and attention to detail More ❯

with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design languages such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience with assertions (e.g., SVA - SystemVerilog Assertions More ❯

higher for Staff level - IP Level/Unit Level verification experience is a must - Experience in designing verification environments for RTL designs - Experience with SystemVerilog and UVM - Understanding of end to end verification processes - UVM knowledge is a bonus - Understanding of computer architecture, such as pipelining, memory systems etc are … offer a fantastic referral scheme which I would be happy to discuss. Keywords: Semiconductors/Verification/CPU/RTL/IP Level/SystemVerilog/C++ #semiconductors #verification #cpu #rtl #ip #systemverilog By applying to this role you understand that we may collect your personal data and store and More ❯