1 to 25 of 80 SystemVerilog Jobs in the East of England

## FPGA Design EngineersApplylocations: GB - Luton - Cap. Green 300: GB - Bristol - Coldharbour Lanetime type: Full timeposted on: Posted Todayjob requisition id: R0024187**Job Description:****Salary Ranges**Engineer: £38k - £53kSenior: £45k - £61kPrincipal: £54k - £71kLead: £60k - £84kLeonardo ...

Job Description:Your impactWould you like to deliver the complex Firmware that forms part of our self-protection systems installed on fast jet, UAV, land and naval platforms? Do you have experience leading Firmware teams ...

addition, your experience will include several of: Digital electronics design, schematics capture and PCB layout FPGA design, RTL development in VHDL/Verilog/SystemVerilog DSP, signal processing and/or related algorithms Analogue electronics, which may include work with sensors, RF or microwave EM Network protocols design and communications ...

Linux and/or Windows development environments . Bonus Experience Xilinx SoC platforms (e.g. Zynq, Versal) Intel (Altera) FPGA architectures, including SoCs Verilog/SystemVerilog Cryptographic algorithms or secure hardware systems Product compliance, certification, or regulated environments Personal Attributes Demonstrates ownership and accountability for technical delivery. Applies a structured approach ...

Experience with state‐of‐the‐art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10) Experience in writing SystemVerilog or VHDL Proven professional experience in at least one of the following areas: Implementation of modern classical decoders on FPGA e.g. LDPC, turbo‐codes; Implementation ...

initial concept through to deployment. They are looking for an FPGA Engineer with the following background: FPGA development experience using VHDL and/or SystemVerilog Experience with Xilinx, Intel, or Microchip FPGA devices Understanding of FPGA verification methodologies and simulation tools Experience with FPGA design toolchains and timing closure Embedded ...

equivalent industry experience). 6+ years' experience in RTL design. Academic or commercial experience in CPU RTL design. Strong RTL design skills using Verilog, SystemVerilog, or VHDL. A solid software engineering background, including experience with: Object-oriented and functional programming paradigms – C,C++,Python Compiler infrastructures, particularly domain-specific languages ...

following background: Strong experience with modern FPGA platforms (e.g. AMD/Xilinx or Intel/Altera devices) RTL coding experience in VHDL, Verilog, or SystemVerilog Background in building or optimising large, complex FPGA or ASIC systems Experience with high-performance, low-latency or deeply pipelined architectures Proven ability to test ...

said, they are looking for the best. Senior FPGA Engineer requirements: Minimum 10+ years commercial FPGA Engineering (Implementation, simulation, verification and test) Coding in SystemVerilog or VHDL FPGA external interface designs (e.g. PCIe, Aurora, Ethernet, SPI etc.) Strong academic background Proactive, collaborative mindset with ownership of projects Resident ...

Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10) Experience in writing SystemVerilog or VHDLProven professional experience in at least one of the following areas: Implementation of modern classical decoders on FPGA e.g. LDPC, turbo-codes; Implementation ...

digital hardware, information engineering, embedded software, control, communications and whole product design. This could include writing software in C for embedded targets, writing SystemVerilog for FPGAs, PCB design and hardware testing. You will be expected to interact directly with clients at all phases of projects, from requirements capture and progress ...

solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard.You'll have:Programming experience, especially with SystemVerilog, VHDL, C(++), Python, Tcl or shell.The ability to imagine and implement improvements to a whole range of processes.The ability to communicate complex technical information ...

constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Programming experience, especially with SystemVerilog, VHDL, C(++), Python, Tcl or shell. The ability to imagine and implement improvements to a whole range of processes. The ability to communicate complex technical ...

from scratch or using shared verification components. Requirements Hands-on experience with at least three projects Experience of creating test benches from scratch, using Systemverilog, Python, or UVM Experience of writing embedded C, ideally for Cortex M-class MCUs Good technical understanding in at least one complex IP protocol,e.g. ...

equivalent), and how an OS‐class subsystem coexists with real‐time domains on the same die. Fluent in the implementation reality of chips — RTL (SystemVerilog), verification methodology (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints. You do not need to be a specialist ...

tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands‐on experience with SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to memory subsystem ...

tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience with SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to memory subsystem ...

looking for an FPGA Engineer with the following background: Proven experience in FPGA or ASIC design and verification RTL coding in Verilog or SystemVerilog Familiarity with Vivado or Quartus and timing closure Understanding of system-level design and high-speed electronics Strong academic background in Engineering, Physics, or a related ...

your experience.Interested? You will naturally have a strong relevant CV with significant commercial-grade experience, demonstrating your skills with Vivado/Quartus and SystemVerilog, Verilog or VHDL. Send it to ECM where it will receive close confidential review. We do read every CV, and try to respond to everyone.Please note ...

cross-functional hardware teams Debug challenging issues spanning RTL, simulation, and hardware platforms What they’re looking for Strong hands-on expertise in SystemVerilog and UVM Proven debugging skills across RTL, simulation, and hardware Experience owning verification planning and strategy in commercial environments Comfortable operating in fast-moving environments with ...

architectures Integration of operating system-class subsystems alongside real-time domains A strong appreciation of the practical realities of chip implementation, including RTL design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints. Familiarity with scripting languages such as Bash, Python ...

protocols.Provide technical mentorship and support to less experienced engineers.Required Skills and Experience5+ years of experience in IP, subsystem, or SoC verification.Strong proficiency in SystemVerilog and Verilog.Experience with UVM or other industry-standard verification methodologies.Experience developing constrained-random verification environments and reusable verification components.Experience developing verification strategies and test protocols.Understanding ...

like side‐channel or fault attacks. Excellent collaboration, communication, and documentation skills. Nice To Have: Familiarity with hardware design flows (e.g., RTL, UVM/SystemVerilog). Exposure to TPMs, Secure Elements, or hardware‐backed crypto modules. Background in academic research or industry work in embedded security, firmware, or cryptographic implementation. ...

complex SoC developmentExperience in static design checks, including CDC, RDC, X-prop, Lint and UPF static checksExperience creating design specificationsExperience with Verilog/SystemVerilog and verification methodologiesStrong delivery record of sophisticated RTL subsystems in reasonable timescalesAbility to navigate and make high-level analysis driven PPA trade-offs along with driving ...

drive root-cause analysis of issues identified throughout the verification process.Required Skills and Experience :Experience building verification environments for sophisticated RTL designs.Strong proficiency in SystemVerilog and scripting languages such as Python, Perl, or Tcl.Proven grasp of the complete verification process, starting from test planning and continuing through to verification closure.Ability ...