19 of 19 SystemVerilog Jobs in the East of England

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

Principal Firmware Engineer Luton Paying up to £80p/h (Umbrella) Responsibilities : Artificial Intelligence, including machine learning and genetic algorithms Auto-generated code using model driven engineering using MATLAB and Simulink tools Design tools such ...

Our client is seeking FPGA Firmware Engineers for contracts based in Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx ...

/GPU design techniques and tools What we’re looking for Essential Strong background in digital IC design methodologies Hands-on RTL design experience (SystemVerilog) at IP or SoC level Experience optimising designs for performance-critical silicon Familiarity with ASIC and/or FPGA design flows Strong analytical mindset ...

closely related field Minimum of 4 years of relevant industry experience Special Requirements Universal Verification Methodology TCL and Bash scripting Formal verification techniques SystemVerilog Salary and benefits £50,000 – £60,000 per annum base salary, dependent on experience and skill set Bonus and/or equity participation available Industry-standard ...

Waveform viewers, and Formal Proof Tools. Familiarity with Formal Verification, Assertions, and Silicon bring-up. Keywords: CPU Verification/Design Verification/DV/SystemVerilog/UVM/Cache Coherence/Branch Prediction/Formal Verification/RIS/SOC/Assembly/Cambridge/Silicon Bring ...

execution Address translation/MMU Experience with random instruction sequencing (RIS) Proven ability to verify designs at block, subsystem, and chip level Proficiency in SystemVerilog, UVM, assertions, and coverage-driven verification Desirable Experience leading or mentoring verification engineers Exposure to formal verification and/or post-silicon bring-up Familiarity ...

Stevenage Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage strategies Mentor engineers and drive best practic click apply for full job details ...

relevant experience needed for this role can be found in the full description below. What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop xxuwjjq verification plans, tests, and coverage strategies Mentor engineers and drive best practic... ...

close coverage, and uncover deep functional bugs Required Skills & Experience Strong hands-on experience with formal verification tools Advanced proficiency in writing and debugging SystemVerilog Assertions Proven ability to tackle complex proof challenges and drive formal closure Experience with complementary formal flows such as: Design Property Verification (DPV). ...

Our client is seeking FPGA Firmware Engineers for contracts based in Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Please ensure you read the below ...

edge sign-off methodologies. Key requirements: Mastery of industry-standard formal tools (e.g., JasperGold, VC Formal, or Questa Formal). Hands-on expertise writing SystemVerilog Assertions. PExperience in deep bug-hunting, coverage closure, and achieving formal sign-off on complex IPs. Knowledge of GPU architectures or sequential equivalence checking ...

Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

Design Verification Engineer This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on ...

Lead the creation and verification of reusable RTL components A well-established company is seeking an RTL Design Architect with strong expertise in verification and good management skills to join their Cambridge-based development team. ...

Design Verification Engineer - CPU DV/Microprocessor Verification/SystemVerilog/UVM We are partnered with a global semiconductor company with a major engineering presence in Cambridge. They are looking for a CPU Design Verification Engineer to work on high performance CPU and SoC products across a broad range ...

open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage strategies Mentor engineers and drive best practices Collaborate with partners to support successful tapeouts Contribute … test and CI infrastructure Requirements: 8+ years in digital design verification with leadership experience Strong SystemVerilog/UVM skills Full verification lifecycle experience through tapeout C and/or Python for test automation Git/GitHub and team collaboration experience Nice to Have: Formal verification, RISC-V/ISA experience ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5+ years industry experience in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience Security ...