23 of 23 SystemVerilog Jobs in Midlothian

development stage): Hardware requirements, capture and management Concept development for complex functions and systems FPGA design, implementation, and analysis Applying verification techniques usingVHDL or SystemVerilog, with exposure toUVMwhere applicable Production of material for design reviews Development of test planning, integration, and design verification activities Ensuring all firmware designs comply with ...

latest FPGA and SoC technologies. They are looking for an FPGA Engineer with the following background: Strong FPGA development experience using VHDL, Verilog, or SystemVerilog Experience with Xilinx, Microchip (Microsemi), or Lattice FPGA devices Knowledge of FPGA verification, timing closure, and embedded systems Experience working with SoC architectures and hardware ...

Depending on your experience, youll bring some, or all, of the following: Experience in design techniques using VHDL Experience in verification techniques using eitherVHDLor SystemVerilog/UVM. Experience in specifying timing and area constraints forefficientFPGA place and route. Ability toanalysesystem level requirements and derive detailedfirmwarerequirements. Degree (BSc, BEng, MEng ...

Computer Science, or a related field Skills and Experience: Required 10+ years of experience in ASIC/SoC design Strong expertise in Verilog/SystemVerilog (or VHDL) Proven experience delivering complex digital hardware systems to silicon Solid understanding of microarchitecture and hardware/software trade-offs Experience with industry-standard ...

level ASIC verification. Strong experience with UVM testbenches and SystemVerilog. Proficient in debugging RTL and firmware using industry-standard simulation tools. Experience with Verilog, SystemVerilog, C, and C++. Experience developing UVM-based verification frameworks, reusable components, and verification methodologies. Experience with Python, Perl, Shell, Makefiles, or similar scripting languages. Familiarity ...

automation initiativesMinimum Qualifications:BS in Electrical or Computer Engineering (or equivalent)4+ years of experience in ASIC/SoC digital designProficiency in Verilog/SystemVerilog and scripting languages (Python, C)Familiarity with RTL-to-GDS flows (e.g., Genus, Innovus, Tempus, Conformal)Understanding of DFT concepts and basic test strategiesWorking knowledge ...

discipline) with an extensive proven background in digital CMOS circuit design Implementation of complex digital circuits and sub-systems in RTL using Verilog/SystemVerilog Understanding of digital system-level design, including use of standard bus protocols, bus architecture design and chip-level clock and reset architectures Verification of block ...

system levelDesirableDevelopment of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or BIndependent verification using SystemVerilog/UVMRelevant experience in the Aerospace or Defence industryExperience of embedded processor cores (e.g. ARM) in FPGA designsFamiliarity with latest FPGA device familiesPractical experience with agile … system levelDesirableDevelopment of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or BIndependent verification using SystemVerilog/UVMRelevant experience in the Aerospace or Defence industryExperience of embedded processor cores (e.g. ARM) in FPGA designsFamiliarity with latest FPGA device familiesPractical experience with agile ...

success with complex mixed signal IC’s.Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysisSystemVerilog - SVA (SystemVerilog Assertions)Testbench design with verification frameworks like UVM/OVM, e, VMMDebugging skills - RTL - Testbench, OOP - Gate level (including SDF)Strong ability to interpret results ...

problem solver.Preferred Skills and Qualifications: Scripting experience with Python, sh/csh, TCL, MakeObject orientated programming (OOP) - Use of OOP design patternsKnowledge of SVA (SystemVerilog Assertions)Metric driven verification - verification planning, requirements extraction - Directed and constrained random verificationFunctional and code coverage analysisPower aware verification (using CPF/UPF)Testbench design ...

diagnosis. Experience with industry-standard EDA tools such as: Siemens Tessent Synopsys TetraMAX/TestMAX Strong scripting skills in Tcl & PythonFamiliarity with Verilog/SystemVerilog and simulation environments Excellent debugging and problem-solving skillsGood communication and excellent collaboration skills.This position is based in our Edinburgh office, UK. This ...

degree in Electrical Engineering, Computer Engineering, or similar field At least ten years’ of experience in analog/mixed-signal verification Proficiency in Virtuoso, SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium) A solid understanding of mixed-signal designs Experience with scripting languages (Python, Perl, Tcl) for automation Excellent ...

Bachelor’s, Master's or PhD degree in Electrical Engineering (or related discipline) Comprehensive understanding of digital circuit design in RTL using Verilog and SystemVerilog Knowledge and understanding of verification of block-level digital designs Experience and understanding of synthesis and timing analysis of digital circuits Knowledge of design ...

Job Description:Salary: 60,000 to 84,955Leonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

Job Description:Salary: Engineer: 37,400 to 53,550/Senior: 45, 200 to 61,950/Principal: 53,300 to 71,400/Lead: 59,400 to 84,955Leonardo UK operates a grade-based ...

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

Edinburgh, ScotlandHardware & Software – Hardware/Full Time/HybridFor over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative ...

other verification engineers to deliver high-quality silicon solutions.ResponsibilitiesDevelop and execute comprehensive verification plans for complex mixed-signal ASIC designs.Create and maintain testbenches using SystemVerilog/UVM.Write and debug test cases to verify functionality, performance, and corner cases.Perform block-level and full-chip verification, including simulation, coverage analysis, and regression … degree in Electrical Engineering, Computer Engineering, or related field.10+ years of experience in digital and/or mixed-signal design verification.Strong proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium).Solid understanding of digital design fundamentals, RTL design, and ASIC development flows.Experience with scripting languages (Python, Perl ...

design best practices.QualificationsEducation:BEng in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.Experience:• Deep knowledge of hardware and digital design fundamentals.• Strong SystemVerilog knowledge.• Experience with SoC integration.• Prior experience on complex RTL designs such as high‐speed I/O, CPUs, accelerators, or complex network‐on‐chip … architecture, verification, software, and system teams.• Ability to work effectively with internal and external stakeholders.• Ability to provide technical input during design reviews.Technology Stack:• SystemVerilog• Python scripting or programming• MATLABPhysical Requirements• Ability to work in a standard office environment and use a computer for extended periods.• Occasional travel ...

designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … continuous improvement of design and verification best practices Qualifications 5+ years’ experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting ...

development lifecycle. This is a hands-on verification role covering everything from planning and testbench development through to coverage closure and debugging. Responsibilities Develop SystemVerilog and UVM verification environments Create reusable verification components and testbenches Write assertions and functional coverage Debug complex RTL and simulation issues Drive verification activities from … sign-off Work closely with cross-functional engineering teams Help improve verification methodology and best practice About You You'll ideally have experience with: SystemVerilog UVM ASIC or SoC Verification Functional Coverage SystemVerilog Assertions (SVA) RTL Debug Verification Planning Experience within automotive or safety-critical semiconductor development would be beneficial ...

plus bonus and RSUs on top. The role Lead and mentor a small verification team Define and execute verification strategy (UVM/SystemVerilog) Oversee functional + formal verification Collaborate with design & architecture teams Drive coverage, quality, and delivery What you’ll bring Strong design verification background (digital or mixed-signal … Experience leading small teams or projects Skills in SystemVerilog, UVM, assertions, coverage Exposure to mixed-signal/ASIC environments (RNM a bonus) Why join Work on globally deployed technology Clear path into technical leadership Relocation support available High-impact role in a growing, innovative business Who this suits Senior Engineers ...