1 to 25 of 49 SystemVerilog Jobs in Scotland

DAL A/B. Experience in Electronic Warfare or RF Systems. Defense or Aerospace industry experience. Development and certification of airborne equipment. Experience with SystemVerilog/UVM for verification. Knowledge of embedded processor cores (e.g., ARM) in FPGA designs. Qualifications: Honours degree or equivalent in Electronics Engineering or another STEM More ❯

Experience Defence domain experience or relevant experience in the Aerospace industry Development and certification of airborne equipment New Product Introduction experience Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Qualifications Honours degree or equivalent in Electronics Engineering or another STEM-based subject More ❯

Desirable Development of real-time, embedded, safety-critical FPGA, preferably in accordance with RTCA/DO-254 DAL A or B Independent verification using SystemVerilog/UVM Relevant experience in the Aerospace or Defence industry Experience of embedded processor cores (e.g. ARM) in FPGA designs Familiarity with latest FPGA device More ❯

/documentation Desirable Development of real-time, embedded, safety-critical firmware, preferably in accordance with RTCA/DO-254 DAL D Independent verification using SystemVerilog/UVM Relevant experience in the Aerospace or Defence industry Experience of embedded processor cores (e.g. ARM) in FPGA designs Familiarity with latest FPGA device More ❯

of high-performance, low-power digital hardware for advanced communication systems and signal processing applications. Key Responsibilities Design and implement efficient RTL (VHDL/SystemVerilog) for DSP algorithms such as filters, transforms, and modulators. Collaborate with algorithm and architecture teams to translate high-level DSP models into optimized hardware implementations. More ❯

of high-performance, low-power digital hardware for advanced communication systems and signal processing applications. Key Responsibilities Design and implement efficient RTL (VHDL/SystemVerilog) for DSP algorithms such as filters, transforms, and modulators. Collaborate with algorithm and architecture teams to translate high-level DSP models into optimized hardware implementations. More ❯

of high-performance, low-power digital hardware for advanced communication systems and signal processing applications. Key Responsibilities Design and implement efficient RTL (VHDL/SystemVerilog) for DSP algorithms such as filters, transforms, and modulators. Collaborate with algorithm and architecture teams to translate high-level DSP models into optimized hardware implementations. More ❯

of high-performance, low-power digital hardware for advanced communication systems and signal processing applications. Key Responsibilities Design and implement efficient RTL (VHDL/SystemVerilog) for DSP algorithms such as filters, transforms, and modulators. Collaborate with algorithm and architecture teams to translate high-level DSP models into optimized hardware implementations. More ❯

of high-performance, low-power digital hardware for advanced communication systems and signal processing applications. Key Responsibilities Design and implement efficient RTL (VHDL/SystemVerilog) for DSP algorithms such as filters, transforms, and modulators. Collaborate with algorithm and architecture teams to translate high-level DSP models into optimized hardware implementations. More ❯

working in a start-up environment and making a significant impact on innovative imaging systems. Requirements Experience with RTL Design using VHDL, Verilog, or SystemVerilog Scripting knowledge with Python, Perl, or Tcl RTL verification experience (desirable) Experience with FPGA prototyping (valuable) Benefits In return, you will receive a competitive salary More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

help build low-latency/high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of More ❯

levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such as More ❯

on your experience, you'll bring some, or all, of the following: Experience in design techniques using VHDL Experience in verification techniques using eitherVHDLor SystemVerilog/UVM. Experience in specifying timing and area constraints forefficientFPGA place and route. Ability toanalysesystem level requirements and derive detailedfirmwarerequirements. Degree (BSc, BEng, MEng, MSc More ❯

Techniques Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC26262, DO 254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python We're an equal opportunities employer. We're committed to developing a diverse workforce and an inclusive working environment. We believe that people More ❯

based in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Define concepts for digital SoC architecture and blocks Create specifications Design and verify RTL (SystemVerilog/VHDL/FPGA) Collaborate closely with analog IC designers and subcontractors Experience with synthesis, timing closure, and STA is highly desirable Support DfT strategy More ❯

Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO‐254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary ( offered depends on level of experience) and other benefits including pension, life assurance and More ❯

Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary ( offered depends on level of experience) and other benefits including pension, life assurance and More ❯

systems in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar More ❯

managing development activities throughout the project lifecycle, and delivering solutions. The candidate will provide technical guidance on FPGA design and verification techniques, including VHDL, SystemVerilog, and UVM. This position is primarily office-based, utilizing display screen equipment, with occasional work in labs and production environments. Depending on security requirements, remote More ❯

systems in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar More ❯

systems in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar More ❯

systems in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar More ❯

systems in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar More ❯