10 of 10 SystemVerilog Jobs in Newport

and test plan, run regressions, reproduce, and debug functional and performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications UVM expertise Please note: You must have full UK working rights to be considered for this More ❯

track issues to resolution. Develop and maintain automated regression test infrastructure and gatekeepers. Requirements Deep expertise in industry-standard verification methodologies, including proficiency with SystemVerilog and UVM. Ability to think creatively about solutions outside of UVM. Experience with high-speed networking interfaces and protocols like PCIe, SERDES or Ethernet. Demonstrated More ❯

Firmware/FPGA Engineer Location: Multiple locations across the UK (Bristol, Bedfordshire, London, Essex) Contract Type: Inside IR35 Clearance: British Sole Passport Holder and SC Cleared or SC Clearable. Who: A leading services company specializing in Defence systems dedicated to More ❯

Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill - Good Communication and More ❯

K&K Social Resources & Development GmbH is an international recruiting agency that has been providing technical resources in the European region since 1993. This position is with one of our clients in the United Kingdom who is actively hiring candidates More ❯

Role - DV Engineer Location:EU/Remote Mandatory Skill: IP/SOC verification Verilog, System Verilog, UVM Code Coverage, functional coverage Industry Experience : 5 to 10 years SOC Verfication Experience on ARM Ecosystem PCIE Experience and also PCIE-VIP usage More ❯

Senior Digital Design Engineer Bristol or Oxford – 3 days onsite £75,000 - £95,000 DOE An exciting opportunity has arisen for a Senior Digital Design engineer to make the next step in their career and join an industry leading company More ❯

investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage … concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard More ❯

Required Skills & Knowledge: Micro-architecture design RTL coding in System Verilog for aviation project Synthesis using Design Compiler/Fusion compiler 5 years SDC development LEC failure debugs RTL/gate level debug experience using tools such as Verdi More ❯

Role - RTL Design/LeadLocation:EU/Remote Mandatory Skill: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog/System Verilog Industry Experience : 5 to 10 years SoC Design engineer with experience working on SOCs based More ❯