2 of 2 SystemVerilog Jobs in South Wales

exciting opportunity for a Senior Staff Verification Engineer to join a global R&D organisation. In this role, you will be responsible for developing SystemVerilog UVM testbench environments for IP-level verification, as well as designing and implementing new UVM verification components. You will ensure that verification environments meet … verification strategy and testbench architecture across the business. Key Requirements Minimum of 7 years' experience in hardware verification, ideally at IP level, using SystemVerilog and UVM Advanced expertise in UVM, SystemVerilog, and SystemVerilog Assertions (SVAs) Experience developing verification platforms and frameworks Proven ownership of IP verification, including delivery against defined ...

Design Verification Engineers to join the team and help ensure first-silicon success. What You'll Do Verify AI accelerator and SoC designs Build SystemVerilog/UVM testbenches and verification environments Perform coverage-driven and assertion-based verification Debug hardware-software interactions and collaborate with architecture, RTL, and software teams … Develop scalable verification frameworks from simulation to post-silicon What We're Looking For Experience in digital IC design verification (SystemVerilog/UVM) Knowledge of Python/C++ (Perl/TCL a plus) Understanding of computer architecture, memory hierarchies, and bus protocols (AMBA/AXI, NoC) Bachelor's or Master ...