2 of 2 SystemVerilog Jobs in Oxfordshire

and skills Bachelor’s or Master’s degree in Electronic Engineering (or related field) Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity More ❯

and skills Bachelor’s or Master’s degree in Electronic Engineering (or related field) Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity More ❯