10 of 10 SystemVerilog Jobs in Wales

Social network you want to login/join with: Aion Silicon is looking for an experienced Verification Engineers to join our office in Theale/Bristol. In this hands-on technical role, you will contribute to a variety of SoC More ❯

performance, low power, and scalability. You will work closely with cross-functional teams including RF, firmware, verification, and architecture. Key Responsibilities Design and implement digital logic in Verilog/SystemVerilog for Wi-Fi MAC/PHY and related IP blocks Collaborate on micro-architecture definition and specifications Drive RTL design from concept through synthesis and verification to GDSII Work with … Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field 5+ years of hands-on ASIC design experience Strong RTL design skills using Verilog or SystemVerilog Experience in SoC development and integration Familiarity with Wi-Fi, wireless MAC/PHY, or DSP-based systems is a plus Good scripting skills (Python, Perl, or TCL) Excellent communication More ❯

performance. What We’re Looking For in a Design for Test (DFT) Engineer: Proven Expertise in DFT engineering, with a strong record of technical innovation. Technical Proficiency : Skilled in SystemVerilog RTL, TCL, Python, and Unix/Linux environments. Core DFT Competencies : Experience with hierarchical scan, memory BIST, JTAG/IJTAG, at-speed testing, ATPG, fault simulation, and silicon debug. Tools More ❯

Social network you want to login/join with: Design Verification Engineer, Newport, Wales Client: IC Resources Location: Newport, Wales, United Kingdom Job Category: Other EU work permit required: Yes Job Views: 1 Posted: 31.05.2025 Expiry Date: 15.07.2025 Job Description More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

and with top-tier industry partners. Key Responsibilities: Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems. Develop high-quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital tools for synthesis, STA, and More ❯

and with top-tier industry partners. Key Responsibilities: Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems. Develop high-quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital tools for synthesis, STA, and More ❯

Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯

Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing More ❯

Social network you want to login/join with: At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking an experienced RTL Engineer to join our client's team. Our mission is to be More ❯