Senior RTL Design Engineer – PCIe Subsystems
- Hiring Organisation
- ARM
- Location
- Sheffield, South Yorkshire, United Kingdom
- Salary
- £ 60 K
timing constraints and exceptions, define design partitions, and support engineering change orders (ECOs) through to tape-out.Required skills and experienceHands-on working knowledge of SystemVerilog or Verilog HDL for RTL designSolid understanding of RTL design techniques for complex SoC developmentFamiliarity with industry-standard EDA tools and methodologiesExperience in the following ...