21 of 21 SystemVerilog Jobs in England

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

aerospace-grade sensing for commercial markets. Key skills of the FPGA Engineer: Experience in FPGA design and system integration (Xilinx/Zynq preferred) Proficient in RTL design (Verilog/SystemVerilog/VHDL) Strong experience with Vivado and SoC development flows Background in designing and tuning real-time control loops (PLLs, PI, etc.) Comfortable debugging in the lab with ILA, scopes More ❯

strategies, and Agile development practices. Work closely with software and ML engineers to deliver efficient, scalable inference applications. Were looking for someone with: 5+ years experience writing well-documented SystemVerilog/Verilog/VHDL. Strong FPGA toolchain knowledge (Quartus, Vivado, or equivalent). Experience in debugging, bring-up, and timing optimisation of FPGA designs. Exposure to C/C++ or More ❯

be the right fit. FPGA Engineer requirements: Minimum 3+ years commercial FPGA Engineering (Implementation, simulation, verification and test) Excellent academic background with degree from a top university Coding in SystemVerilog or VHDL FPGA external interface designs (e.g. PCIe, Aurora, Ethernet, SPI etc.) Some exposure to digital signal processing Proactive, collaborative mindset with ownership of projects This is a rare chance More ❯

Required Skills and Experience: BSc, MSc or PhD degree qualification in Electronics/Computer Engineering or equivalent Ability to understand and use Hardware Description Languages (HDLs) such as Verilog, SystemVerilog or VHDL Strong interest in and understanding of CPU architectures and SoC design principles Experience in using RTL simulation tools for debugging purposes Ability to learn and communicate IP product More ❯

FPGA Engineer/Senior FPGA Engineer My client, a trailblazer in advanced security technology, excels in creating high-integrity critical systems where flawless performance is non-negotiable. They continually push boundaries to exceed customer and stakeholder expectations, making excellence their More ❯

ensure end-to-end performance and compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low-level C software for FPGA bring-up, test, and integration. Use industry-standard tools such as Vivado, Quartus, and ModelSim for simulation … reviews, solution development, and internal consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real-time, high-speed, or RF-centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm-to-hardware workflows. Proven ability to develop and deploy on More ❯

ensure end-to-end performance and compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low-level C software for FPGA bring-up, test, and integration. Use industry-standard tools such as Vivado, Quartus, and ModelSim for simulation … reviews, solution development, and internal consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real-time, high-speed, or RF-centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm-to-hardware workflows. Proven ability to develop and deploy on More ❯

Principal Firmware Engineer Luton Paying up to £80p/h (Umbrella) Responsibilities : Artificial Intelligence, including machine learning and genetic algorithms Auto-generated code using model driven engineering using MATLAB and Simulink tools Design tools such as Xilinx, TCL, Verilog, System More ❯

and space-qualified ASICs. As an FPGA Engineer, you will: Translate complex signal processing algorithms into efficient RTL architectures Design and verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills required for … the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the position of More ❯

and space-qualified ASICs. As an FPGA Engineer, you will: Translate complex signal processing algorithms into efficient RTL architectures Design and verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills required for … the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the position of More ❯

D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. … in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such More ❯

D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. … in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such More ❯

data analysis. "Nice To Have" Skills and Experience : Experience with SoC-level performance analysis and tools. Familiarity with memory subsystem micro-architecture and performance implications. Experience with Verilog/SystemVerilog RTL, including analysis and debugging in collaboration with design teams. Working knowledge of AMBA protocols and transaction-level modeling (SystemC/TLM). Exposure to Verilog/SystemVerilog and interaction More ❯

Microarchitect & RTL Design Engineer Cambridge,/Bristol England, United Kingdom We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified More ❯

Microarchitect & RTL Design Engineer Cambridge,/Bristol England, United Kingdom We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯