DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design tools (P&R). Proficiency in SystemVerilog, C, SystemC, C++, Python, Perl, or TCL. Knowledge of place and route methodologies. Strong communication skills, both written and spoken, in English. Who we are More ❯
speed I/O like GTM and F-Tile transceivers Expertise in FPGA tool flows: synthesis, partitioning, place & route, timing analysis Strong skills in SystemVerilog, Verilog, VHDL, and scripting (tcl and Python) Experience with high-performance FPGA devices such as Xilinx Versal Premium or Intel Agilex 7 If you're More ❯
embedded C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power More ❯
Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working More ❯
implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯
implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯
implementation and testing, support. Proven technical and/or team leadership skills. Practical experience of working on microprocessor designs. Desirable experience: Working knowledge of SystemVerilog Assertions (SVA). Mentoring team members. Knowledge of scripting eg Python, Perl or unix shell scripting. Knowledge of assembly language (preferably ARM), C/C++ More ❯
lifecycle - from requirements definition and architectural design to implementation, testing, and integration. What You'll Bring Proficiency with tools such as Xilinx, TCL, Verilog, SystemVerilog, and UVM. Experience with FPGA architectures including Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel). Knowledge of high-speed interfaces such as PCIe More ❯
Manchester, Lancashire, United Kingdom Hybrid / WFH Options
Arm Limited
embedded C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power More ❯
lifecycle - from requirements definition and architectural design to implementation, testing, and integration. What You'll Bring Proficiency with tools such as Xilinx, TCL, Verilog, SystemVerilog, and UVM. Experience with FPGA architectures including Xilinx 7, Xilinx UltraScale, Intel (Altera), or Microsemi (Actel). Knowledge of high-speed interfaces such as PCIe More ❯
IC Design expertise – Solid knowledge of ASIC/FPGA design techniques and methodologies. Hands-on RTL Design – Experience at IP or SoC level using SystemVerilog, C++, Python, Perl, or TCL . Verification Knowledge – Familiarity with UVM, formal verification, assertions, and coverage bins . Experience with GPU/CPU design – Understanding More ❯
language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯
language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯
language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯
or choose to work from one of their hubs in cities like London or Dubai. What We're Looking For Proficiency in Verilog/SystemVerilog with experience in FPGA design. Hands-on expertise with Xilinx Vivado, Altera Quartus, and FPGA debugging tools (ILA, SignalTap). Experience in peripheral integration (10G More ❯
london, south east england, united kingdom Hybrid / WFH Options
Durlston Partners
or choose to work from one of their hubs in cities like London or Dubai. What We're Looking For Proficiency in Verilog/SystemVerilog with experience in FPGA design. Hands-on expertise with Xilinx Vivado, Altera Quartus, and FPGA debugging tools (ILA, SignalTap). Experience in peripheral integration (10G More ❯
Instruments LabVIEW-based equipment. Performing hands-on testing of devices using National Instruments LabVIEW-based equipment in the Plymouth lab facility. Designing and verifying SystemVerilog RTL targeting FPGA implementations. Creating schematics for test boards and fixtures. Recording and analyzing product test results and equipment logs. The Impact You Will Have More ❯
Ideally you will have familiarity with the following technologies: RTL FPGA development in VHDL. Programming in Python and C/C++. Verification using VHDL, SystemVerilog and/or Python. Network packet processing and network protocols (ethernet, IP, UDP, TCP ...) Signal processing in FPGAs. Cryptographic algorithms, implementations and applications in More ❯
determine verification requirements from the analysis of specifications Experience of debug and testing methodologies Experience with industry-standard verification methodologies and tools (UVM/SystemVerilog, Tools like VCS/Cadence/Questa) Experience in version control systems (e.g., Git/Mercurial/Perforce/Subversion) You might also have: A More ❯
Engineering, or a related field Experience developing applications in Python Familiarity with open-source development best practices and community building Familiarity with Verilog/SystemVerilog and EDA tool flows, particularly those used for design verification Strong teamwork and communication skills Preferred Qualifications (not required): Experience working on (or working closely More ❯
Engineering, or a related field Experience developing applications in Python Familiarity with open-source development best practices and community building Familiarity with Verilog/SystemVerilog and EDA tool flows, particularly those used for design verification Strong teamwork and communication skills Preferred Qualifications (not required): Experience working on (or working closely More ❯
of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of a design block Analytical thinking, self-sufficiency and team collaboration skills Ability to work effectively across More ❯
of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of multiple design blocks Analytical thinking, self-sufficiency and strong team collaboration skills Ability to work effectively More ❯
feedback and who can independently define the scope of work. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. You have formal verification experience. What you can expect from us More ❯
