4 of 4 Tcl Jobs in London

FPGA Design Engineer (Edinburgh)

Hiring Organisation
Sanderson Recruitment
Location
London, England, United Kingdom
detail.Ability to work effectively within multidisciplinary teams and liaise directly with clients.Desirable:Familiarity with version control systems (e.g., Git, SVN).Scripting experience in TCL or Python for tool automation.Additional Information: Due to the sensitive nature of the work, successful candidates must be eligible for UK Security Clearance. Pre-employment screening ...

Formal Verification Engineer - Semiconductors (Northampton)

Hiring Organisation
Technical Futures
Location
London, England, United Kingdom
discipline.5+ years experience of working within the semiconductor industry.Proven experience in the Verification of complex designs - FPGA or ASIC.Good scripting skills (Python, Perl or TCL for automation).Working with RTL designers to develop a formal micro-architecture specification.In-depth understanding of Formal Verification techniques.Strong knowledge on Metrics-driven verification including ...

Digital EDA Engineer - Semiconductors (Reading)

Hiring Organisation
Technical Futures
Location
London, England, United Kingdom
systems globally. Key skills and experience should include:Bachelors/Masters Degree in Electronic/Computer/Electrical Engineering.Programming skills in Python, Shell, Perl, Tcl or similar.Deep understanding of the chip design process.Proficiency building robust EDA/CAD flows.Experience with Cadence Voltus (or similar).Extensive experience across front ...

Senior IP Design Engineer Contract Remote (UK) (Belfast)

Hiring Organisation
DCV Technologies Limited
Location
London, England, United Kingdom
role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.Key ResponsibilitiesDesign high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoCDeliver synthesis-ready RTL meeting timing … integration requirementsImplement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocksDrive timing closure using Vivado toolchainsDevelop automation using Python/Tcl scriptingCollaborate with hardware, SoC, firmware and integration teamsEssential SkillsStrong SystemVerilog RTL design experienceFPGA/Adaptive SoC design flow: synthesis, P&R, timing closureHigh-speed digital interfaces: 100GbE/ ...