verification HLS or other DSP flow experience for FPGA Comfortable attacking new and unfamiliar problems Interest in trading Things we would like to see but are not essential: Python, TCL Low latency design ASIC Network and packet processing Trading systems WHAT WE OFFER Competitive compensation Annual discretionary bonus Fully catered breakfast, lunch and snacks. 25 days annual leave Informal dress More ❯
low-power design methodologies, power optimisation techniques, and multi-power domain architectures. Expertise in timing closure, signal integrity, IR drop analysis, and formal verification. Proficiency in scripting languages like TCL, Perl, or Python for automation. Excellent problem-solving skills, communication, and teamwork in a collaborative design environment. Experience in high-performance computing (HPC), AI accelerators, or networking chips. Create a More ❯
graphics pipelines and/or neural network accelerators Awareness of physical design implications (DFT, timing, floorplanning) Proficiency with EDA tools (Synopsys, Cadence, Mentor, etc.) Strong scripting skills in Python, TCL, or similar BS/MS in Electrical Engineering, Computer Engineering, or related field Verification Requirements: 5+ years of experience in hardware verification (complex SoCs preferred) Strong understanding of UVM and … coverage, assertions, formal) Familiarity with RISC-V and GPU/AI architectures (preferred) Proficient with simulators and debug tools (e.g., VCS, Questa, ModelSim) Scripting experience in Python, Perl, or TCL Strong analytical and debugging skills BS/MS in Electrical Engineering, Computer Engineering, or related field Get in touch with for Digital Design Get in touch with for Verification And More ❯
