Senior Digital Verification Engineer
- Location
- Glasgow, Scotland, United Kingdom
MSc., degree in Electronics or Electrical Engineering.* Strong hands-on experience with **SystemVerilog** for testbench development and verification.* Proven expertise in **UVM (Universal Verification Methodology)**, including component creation, sequences, drivers, monitors, and scoreboards.* Solid understanding and practical use of **Constrained Random Verification** techniques.* Experience with **Metrics‐Driven Verification**, including functional ...