2 of 2 UVM Jobs in Lancashire

or hardware verification languages e.g. ( SystemVerilog), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case More ❯

the team Required Skills and Experience: Experience in working with constrained-random verification including ownership of complex verification environment Experience of using SystemVerilog and UVM Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms Competent in developing verification flows, making the best use of EDA More ❯