2 of 2 UVM Jobs in Swindon

environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow. Minimum Qualifications Strong knowledge of … SystemVerilog and UVM Experience developing scalable and portable test-benches Experience with constrained random verification environments MS/BS in Computer Science or Electrical Engineering or equivalent Fluency in English language is required Preferred Qualifications Experience defining coverage space, writing coverage model, analyzing results Experience with Assertion Based Verification Knowledge of Object Oriented Programming Experience in Formal Verification (Formal Linting More ❯

to production and delivery/tape-out, including performance review, analysis, costing, and optimisation Understanding of the product's design & verification needs, standardisation, adherence to frameworks and methodolgies e.g. UVM Excellent communicator, with a keen interest in team collaboration and a clear approach to the design & development process Bonus/"Nice-to-have" skills Digital Video processing/video compression More ❯