Social network you want to login/join with: Aion Silicon is looking for an experienced Verification Engineers to join our office in Theale/Bristol. In this hands-on technical role, you will contribute to a variety of SoC , subsystem , and IP development projects , taking responsibility for the verification process from planning to coverage closure. Working closely … with ASIC/SoC project leaders , you will architect, specify, and lead the implementation of high-level verification projects, using advanced verification languages. You will also collaborate with multi-site development teams and customers to propose solutions and ensure the delivery of high-quality verification environments and methodologies. If you are a passionate and innovative engineer who enjoys solving complex verification problems and leading teams, this could be the perfect opportunity for you. Key Responsibilities: Verification Expertise: Provide hands-on expertise in IP and SoC-level functional verification , including the development of testbenches and implementation of verification plans . Problem Solving: Proactively address and resolve verification challenges, working independently or More ❯
Social network you want to login/join with: Design VerificationEngineer, Warrington, Cheshire Client: ALOIS Solutions Location: Warrington, Cheshire Job Category: Other EU work permit required: Yes Job Views: 5 Posted: 09.06.2025 Expiry Date: 24.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM boot , C code, GNU toolchain ) Write test plans, define test methodologies, develop … test benches, write test cases, complete functional verification, and close coverage for all design blocks in the SoCs/Subsystems. Run regressions, debug test failures, and file bug reports as needed. Develop tests to meet functional and code coverage requirements based on coverage gap analysis. Provide verification reports showing all tests passing on the RTL. Use methodologies including … design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
