Verification Engineer Jobs in Crawley

2 of 2 Verification Engineer Jobs in Crawley

Design Verification Engineer

Crawley, England, United Kingdom
JR United Kingdom
Social network you want to login/join with: Design Verification Engineer, Crawley, West Sussex Client: ALOIS Solutions Location: Crawley, West Sussex, United Kingdom Job Category: Other - EU work permit required: Yes Job Views: 5 Posted: 09.06.2025 Expiry Date: 24.07.2025 Job Description: Verify CPU connectivity to IP blocks (using ASM boot , and C code, GNU toolchain ) The tasks … will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification, and closing coverage for all the agreed design blocks in the SoCs/Subsystems Run regressions, debug test failures, and file bug reports as needed. Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of … coverage gaps. Provide verification reports as needed to show all implemented tests passing on the RTL. Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based testcases. #J-18808-Ljbffr More ❯
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Design Verification Engineer

Crawley, West Sussex, UK
ALOIS Solutions
Design Verification: • Create coverage driven verification plan document. • Create UVM verification environment. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs … test failures and file bug report as needed. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Provide verification report as needed to show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal More ❯
Employment Type: Full-time
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