3 of 3 Verification Engineer Jobs in Wales

Job title: Verification Engineer - Safety-Critical Software Location: Cardiff Job type: Permanent Salary: £70,000 iO are now partnered with a highly specialised, safety-critical engineering firm offering end-to-end solutions within the Aerospace and Defence industries. Currently looking for a Software Verification Engineer to join on a permanent basis to work on some extremely More ❯

Job title: Verification Engineer Learn more about the general tasks related to this opportunity below, as well as required skills. - Safety-Critical Software Location: Cardiff Job type: Permanent Salary: £70,000 iO are now partnered with a highly specialised, safety-critical engineering firm offering end-to-end solutions within the Aerospace and Defence industries. Currently looking for a … Software Verification Engineer to join on a permanent basis to work on some extremely exciting customer projects. This is your chance to get hands-on with technically challenging and meaningful projects that will catapult your career. Key skills: Strong experience developing and verifying embedded C or C++ software Knowledge of safety-critical standards (DO-178C, ISO 26262, or More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯