Senior Design VerificationEngineer Cambridge,/Bristol England, United Kingdom Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they … re looking for passionate individuals to join a seasoned and dynamic team. Senior D esign Verificationengineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define … Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge More ❯
Senior Design VerificationEngineer Cambridge,/Bristol England, United Kingdom Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they … re looking for passionate individuals to join a seasoned and dynamic team. Senior D esign Verificationengineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define … Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge More ❯
Job title: VerificationEngineer - Safety-Critical Software Location: Cardiff Job type: Permanent Salary: £70,000 iO are now partnered with a highly specialised, safety-critical engineering firm offering end-to-end solutions within the Aerospace and Defence industries. Currently looking for a Software VerificationEngineer to join on a permanent basis to work on some extremely More ❯
Subject - Senior Product Verification & Test Engineer Location - Onsite at the Paignton office Salary - Competitive + Benefits Benefits - Annual Bonus, 25 days annual leave (increasing to 30 with length of service), 4 x life insurance, employer pension contributions starting from 6% up to 14%, single private medical insurance and Medicash plan The Client - A global leader in advanced technology … simulation systems, many of which comprise radio frequency signal generators plus computer systems running complex application software; all designed in-house. The Candidate - You will be an experienced Product Verification and Test Engineer, comfortable working with RF lab equipment and test automation. You should bring strong skills in LabVIEW and/or Python, with the ability to troubleshoot … technical issues and deliver solutions to complex problems. A background in digital communications, RF systems, or GNSS is highly desirable. The Role - As a Senior Product Verification & Test Engineer, you will play a key role in the engineering team, focusing on verification and automation of both current and next-generation Positioning test solutions. Duties - Setup and perform More ❯
client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal VerificationEngineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯
client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal VerificationEngineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯
client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal VerificationEngineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯
client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal VerificationEngineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯
Barnsley, South Yorkshire, Yorkshire, United Kingdom
Pin Point Recruitment
Product VerificationEngineer Barnsley, Permanent If youre the kind of person who loves solving problems, digging into the details, and making sure things work exactly as they should, this is your chance to help shape high-quality, reliable products from the ground up. Youll be stepping into a growing team where your work has a direct impact on More ❯
working but does require engineers on site for 4/5 days per week and is a on secure site where SC clearance is needed. As a Validation and VerificationEngineer you'll support product development for the system. Day to day you'll be supporting and producing the definition of the Test Scenarios and success criteria to … ensure the product meet its requirements. The role will also involve production of the appropriate verification plans to agree with the equipment DA the method of verification used. Skills, Qualification and Experience Degree or equivalent qualification in Systems engineering or similar Systems design/systems engineering experience in software-based equipment Hands-on experience of SysML, Rhapsody and … Employees' Choice Awards, 2022, and most recently receiving three accreditation gold standard awards with Investors in People! "Interesting work. Good work-life balance. Employees made to feel valued." Software Engineer, 5 Dec 2022. *Glassdoor review. "Promotes and believes in a good work/life balance interesting work on most programmes Encourages internal mobility. Offers good development/training opportunities More ❯
working but does require engineers on site for 4/5 days per week and is a on secure site where SC clearance is needed. As a Validation and VerificationEngineer you'll support product development for the system. Day to day you'll be supporting and producing the definition of the Test Scenarios and success criteria to … ensure the product meet its requirements. The role will also involve production of the appropriate verification plans to agree with the equipment DA the method of verification used. Skills, Qualification and Experience Degree or equivalent qualification in Systems engineering or similar Systems design/systems engineering experience in software-based equipment Hands-on experience of SysML, Rhapsody and … Employees' Choice Awards, 2022, and most recently receiving three accreditation gold standard awards with Investors in People! "Interesting work. Good work-life balance. Employees made to feel valued." Software Engineer, 5 Dec 2022. Glassdoor review. "Promotes and believes in a good work/life balance interesting work on most programmes Encourages internal mobility. Offers good development/training opportunities More ❯
Our OEM Client based in Gaydon, is searching for a HIL Test VerificationEngineer – Steering to join their team, Inside IR35. This is a contract position until 31st March 2026. Umbrella Pay Rate: £27.03 per hour. Duties: Develop test cases to be executed within the Steering System HIL. Implement existing client Vehicle test procedures in Steering HIL environment. More ❯
Bristol, Avon, England, United Kingdom Hybrid / WFH Options
MBDA
company, to see the full product development life-cycle and deliver real capability to the customers to protect their home nation for the future. As a C2 Validation and VerificationEngineer you'll support product development for the C2 system. Day to day you'll be supporting and producing the definition of the C2 Test Scenarios and success … criteria to ensure the C2 product meet its requirements. The role will also involve production of the appropriate verification plans to agree with the equipment DA the method of verification used. What we're looking for from you: Systems design/systems engineering experience in software based equipment. Degree level qualification (or equivalent experience) Hands-on experience of More ❯
Stockport, Greater Manchester, North West, United Kingdom
Alten Ltd
sustainability. At ALTEN, we empower talented engineers to innovate, solve complex challenges, and deliver impactful solutions that build tomorrows worldtoday. Job Description Join us as a Software Integration and VerificationEngineer , where youll be working hands-on in an embedded defence systems environment . This role is perfect for engineers who thrive on solving real-world challenges, from … On-site in Manchester (5 days per week) Security Clearance: Must be SC clearable (no caveats) Experience Level: 5+ years relevant experience Key Responsibilities: Carry out software integration and verification activities across embedded systems in a defence context Use Bash scripting and strong Linux knowledge to automate and streamline test processes Perform TCP/IP network debugging to diagnose More ❯
sectors. Our capabilities span across a wide range of functions including system integration, design engineering, electronics and electrical systems, and chassis engineering. We are seeking a skilled and adaptable Verification & Validation (V&V) Test Engineer to support the testing and validation of systems and products across both lab environments (rigs, test cells) and test centres (proving grounds, facilities More ❯
