knowledge of RTL synthesis, performance, and power analysis. In-depth understanding of digital design concepts and problem-solving capabilities. Proficient in HDL coding (VHDL, Verilog, SystemVerilog). System design knowledge, including clock domain management, reset schemes, and power management. Experience with SoC level verification (HW/SW co-verification, multi More ❯
planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC More ❯
see: Honours Degree in Electrical Engineering or Computer Science, or equivalent experience 5+ years of proven experience in RTL verification experience Knowledge of HDL (Verilog/VHDL) Experience in building test benches, debugging simulation failures and evaluating/closing coverage Exposure to industry standard verification tools for simulation and debug More ❯
BSD/LBIST/Boundary Scan insertion. ATPG/TC improvements and pattern generation. Pattern simulation (Zdel/SDF) and pattern verification (VCS, NC-Verilog, NC-Sim, ModelSim). Diagnosis of ATE failures and silicon bring-up. Deep understanding of DFT architecture design and implementation. Strong problem-solving skills and More ❯
Title: FPGA Design & Validation Engineer (Anywhere in UK or Europe)- 10+ Years Exp Xilinx, Verilog, Ethernet Location: Remote (anywhere in UK or Europe) Experience: 10+ Years We're hiring FPGA Design & Validation Engineers to work on high-performance systems in Industrial Automation and Ethernet-based Networking click apply for full More ❯
belfast, antrim, united kingdom Hybrid / WFH Options
Dabster
logical equivalency checking (LEC) · Verification debug support · Lint checks – RTL, CDC, RDC, DFT, UPF Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC reset control o Subsystem/SOC clock control o Subsystem/SOC More ❯
show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯
