IP Design Engineer

London, UK OR Belfast, NI. (Person must be willing to travel to Belfast once OR twice in a quarter)

6 Months.

1-2 Days (Flexible Hybrid).

6 Months Fixed Term. (Possible Extension)

DOE

Core Scope:

Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.

Key Skills:

• System Verilog RTL design
• 100Gb Ethernet, PCIe Gen5, AMBA/AXI
• Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure
• Vivado/Vitis expertise
• Python/Tcl scripting
• Git & CI/CD experience

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