Design Verification Engineer

Staff Verification Engineer / Tech Lead

Edinburgh

Compensation: Competitive base salary + bonus + RSUs

Additional Support: Relocation package and visa sponsorship available (if required)

I am seeking a highly skilled and motivated Staff Design Verification Engineer to join a global semiconductor company based in Edinburgh. In this role, you will be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies. You will collaborate closely with architects, designers, and fellow verification engineers to deliver high-quality silicon solutions.

Relocating to Edinburgh offers an excellent balance between career growth and quality of life. As a key UK hub for semiconductor and embedded systems development, the city provides access to impactful ASIC and verification work without the intensity and high cost of living associated with larger tech centres. You’ll have the opportunity to work on real silicon in technically engaged teams, where senior engineers can make a meaningful impact. Beyond work, Edinburgh offers a compact, walkable environment, rich cultural heritage, and easy access to nature—contributing to a more balanced and rewarding lifestyle.

Key Responsibilities

• Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs
• Create and maintain testbenches using SystemVerilog and UVM
• Write and debug test cases to validate functionality, performance, and corner cases
• Perform block-level and full-chip verification, including simulation, coverage analysis, and regression debugging
• Collaborate with design engineers to understand specifications and define verification requirements
• Analyze and resolve issues identified during verification and post-silicon validation
• Mentor junior engineers and contribute to improving verification methodologies and infrastructure
• Participate in code reviews and drive continuous improvement in design and verification practices
• Manage and debug gate-level simulations

Qualifications

• 10+ years of experience in digital and/or mixed-signal design verification
• Strong proficiency in SystemVerilog, UVM, and industry-standard simulation tools
• Solid understanding of digital design fundamentals, RTL design, and ASIC development flows
• Experience with scripting languages such as Python, Perl, or Tcl for automation
• Familiarity with formal verification, assertion-based verification, and coverage-driven methodologies
• Strong analytical and problem-solving skills with attention to detail
• Excellent communication and teamwork abilities
• Experience with version control systems and CI/CD workflows
• Exposure to additional methodologies (e.g., eRM, HW/SW co-simulation) is advantageous
• Knowledge of standard protocols such as AMBA, I2C, etc. is desirable

What’s on Offer

This is an excellent opportunity to join a leading semiconductor company in one of the UK’s most desirable cities. The role offers a competitive compensation package, including a base salary of up to £95,000 (DOE), RSUs, and a performance-based bonus. Relocation assistance and visa sponsorship are available where required.

For more information, please contact Rachel Mason at IC Resources.