Contract RTL Design Engineer
Contract RTL Design Engineer (ASIC) Is your CV ready If so, and you are confident this is the role for you, make sure to apply asap.
- Remote (open to UK and EU based contactors) Location of work: Remote, some on-site preferred (Bristol, Cambridge or Oxford) Rate: Up to £60 per hour, outside IR35 Length: 6 months initially We're looking for an experienced RTL Design Engineer to support the design and verification of a complex digital subsystem for a mixed signal ASIC, including integration of an ARM Cortex core. This is a hands-on contract role, working closely with an established digital and analogue engineering team. The Role: RTL design and verification of a digital subsystem Integration of an ARM Cortex (Cortex-M) core Working on digitally controlled mixed-signal systems Close collaboration with internal engineers Skills and Experience required: Strong RTL design using VHDL (primary) and Verilog Design and testbench development Experience integrating ARM Cortex cores Knowledge of AMBA protocols (AHB, APB) Low-power digital design (clock gating, power gating, retention) Digital interfaces: UART, SPI, IC Simulation tools: QuestaSim / ModelSim xkybehq preferred Ability to interpret lint, CDC, and synthesis reports Python or scripting experience is a plus If you're an ASIC focused RTL engineer (rather than FPGA only) with ARM experience and looking for a technically engaging contract, we'd like to hear from you. A one stage interview can be quickly arranged.
- Remote (open to UK and EU based contactors) Location of work: Remote, some on-site preferred (Bristol, Cambridge or Oxford) Rate: Up to £60 per hour, outside IR35 Length: 6 months initially We're looking for an experienced RTL Design Engineer to support the design and verification of a complex digital subsystem for a mixed signal ASIC, including integration of an ARM Cortex core. This is a hands-on contract role, working closely with an established digital and analogue engineering team. The Role: RTL design and verification of a digital subsystem Integration of an ARM Cortex (Cortex-M) core Working on digitally controlled mixed-signal systems Close collaboration with internal engineers Skills and Experience required: Strong RTL design using VHDL (primary) and Verilog Design and testbench development Experience integrating ARM Cortex cores Knowledge of AMBA protocols (AHB, APB) Low-power digital design (clock gating, power gating, retention) Digital interfaces: UART, SPI, IC Simulation tools: QuestaSim / ModelSim xkybehq preferred Ability to interpret lint, CDC, and synthesis reports Python or scripting experience is a plus If you're an ASIC focused RTL engineer (rather than FPGA only) with ARM experience and looking for a technically engaging contract, we'd like to hear from you. A one stage interview can be quickly arranged.