Senior Verification Engineer - Highspeed Networking

A leader in the design, development manufacturer of Semiconductor, Datacentre equipment & high-performance infrastructure & applications are seeking a senior verification engineer to support the high-speed networking function within the engineering team.

The focus of the role will be on building and maintaining sophisticated, class-based UVM verification environments, driving coverage closure, and supporting SoC-level integration. This role involves close collaboration with design, architecture, software and systems teams to deliver production-ready silicon for demanding networking applications.

Key Responsibilities

• Verify high-speed connectivity IP using advanced SystemVerilog UVM methodologies.
• Develop constrained-random test environments and execute comprehensive verification plans.
• Define test plans and drive functional and code coverage to verification sign-off.
• Integrate and configure verification IP (VIP) for industry-standard protocols.
• Support SoC-level verification, including Embedded processor co-simulation and system-level debug.
• Automate regression testing using Python and CI/CD-based verification workflows.
• Collaborate across hardware and software teams to debug issues and continuously improve verification quality.

Essential Skills and Experience required

• Strong experience with UVM, constrained-random verification and coverage-driven verification sign-off.
• Hands-on verification experience with 100Gb Ethernet, PCIe Gen5, and AMBA/AXI protocols.
• Some proficiency in Python Scripting for automation and regression management within CI/CD environments.
• Experience with adaptive SoC design and verification flows, including Vivado and Vitis.
• Solid understanding of Embedded processor co-simulation, SoC integration and debug in a semiconductor context.