Verification Engineer

JOB AD:

• Rate: Competitive, Inside IR35
• Start Date: ASAP A client of mine based in Cambridge and Bristol is looking for several Verification Engineer to join our client's Verification Team on a 12-month contract. This role is critical in supporting verification efforts to ensure high-quality silicon delivery that meets architectural and design specifications.
• The successful candidate will be involved in functional verification, coverage closure, and diagnostic activities across complex hardware systems.

The Team:

The Verification Team operates within the Design Group and collaborates closely with both the Logical and Physical Design Teams.

The team's mission is to ensure that RTL implementations align fully with architectural specifications for products.

Key Responsibilities:

• Execute verification tasks within the silicon design lifecycle
• Develop and manage verification plans and functional coverage specifications
• Provide feedback to architects and design engineers
• Develop tests and perform failure triage/debugContribute to the shared verification infrastructure and methodology
• Facilitate cross-site communication and collaboration

Skills and Experience:

• Industry experience in silicon/ASIC/CPU verification
• Strong understanding of verification methodologies and planningProven ability to lead, plan, and execute verification tasks independently
• Skilled in debugging complex issues across software/hardware boundaries

Proficient in:

SystemVerilogPython, C++Linux environments Desirable Skills:UVM (Universal Verification Methodology)SVA (SystemVerilog Assertions)

Assembly language familiarityExperience with toolchains such as LLVM or GCCDVCS tools (e.g., Git)Experience with job schedulers (SGE or similar DRMS)XML/XPath/XSLTWeb technologies: HTML/DOM, JavaScript, SQL Working Pattern:Hybrid working: 3 days onsite in Cambridge or Bristol, 2 days remote