Kernel Engineer
Job Title: Principal Kernel Engineer Any additional information you require for this job can be found in the below text Make sure to read thoroughly, then apply.
Our client are an international semiconductor and consumer electronics company.
The Role
Optimize memory management internals: buddy allocator, slab/SLUB, page reclaim and LRU/MGLRU, memory compaction and defragmentation, transparent huge pages, page-fault and TLB-shootdown paths, copy-on-write behaviour
Drive scheduler performance: run-queue and load-balancing behaviour, energy-aware scheduling, wakeup latency, task placement on heterogeneous (big.LITTLE/DynamIQ) topologies, cpufreq/cpuidle governor interaction
Optimize synchronization primitives and lock-heavy paths: futex fast/slow paths, mutexes and rwsems, spinlocks/qspinlocks, RCU, seqlocks, per-CPU data, memory ordering and barriers on ARM64
Analyse and improve IPC and syscall paths: context-switch cost, binder-style IPC, shared memory, vDSO, interrupt/softirq handling
Identify bottlenecks on flagship mobile workloads (gaming, day-of-use, camera, AI inference) using PMU counters, ftrace/perf, eBPF, lockdep/lockstat, and power measurement with mA/mAh attribution
Land production-quality kernel patches from hypothesis through benchmarking to ship, with measured latency and energy impact
Must-Haves
10+ years of OS kernel development in C (Linux or comparable), with patches shipped to production systems at scale
Expert-level understanding of MM internals: physical/virtual memory management, buddy and slab allocation, reclaim, compaction, page tables, xkybehq TLB management
Deep scheduler knowledge: CFS/EEVDF internals, load balancing, preemption, real-time classes, energy-aware scheduling
Mastery of kernel synchronization: locking primitives, RCU, lock-free techniques, the ARM64 memory model and barrier semantics
Proven kernel performance-analysis skills: PMU counters, ftrace/perf, eBPF, lock contention and latency analysis
Strong ARM64 architecture grounding: exception levels, cache hierarchy and maintenance, TLBs, memory ordering
Our client are an international semiconductor and consumer electronics company.
The Role
Optimize memory management internals: buddy allocator, slab/SLUB, page reclaim and LRU/MGLRU, memory compaction and defragmentation, transparent huge pages, page-fault and TLB-shootdown paths, copy-on-write behaviour
Drive scheduler performance: run-queue and load-balancing behaviour, energy-aware scheduling, wakeup latency, task placement on heterogeneous (big.LITTLE/DynamIQ) topologies, cpufreq/cpuidle governor interaction
Optimize synchronization primitives and lock-heavy paths: futex fast/slow paths, mutexes and rwsems, spinlocks/qspinlocks, RCU, seqlocks, per-CPU data, memory ordering and barriers on ARM64
Analyse and improve IPC and syscall paths: context-switch cost, binder-style IPC, shared memory, vDSO, interrupt/softirq handling
Identify bottlenecks on flagship mobile workloads (gaming, day-of-use, camera, AI inference) using PMU counters, ftrace/perf, eBPF, lockdep/lockstat, and power measurement with mA/mAh attribution
Land production-quality kernel patches from hypothesis through benchmarking to ship, with measured latency and energy impact
Must-Haves
10+ years of OS kernel development in C (Linux or comparable), with patches shipped to production systems at scale
Expert-level understanding of MM internals: physical/virtual memory management, buddy and slab allocation, reclaim, compaction, page tables, xkybehq TLB management
Deep scheduler knowledge: CFS/EEVDF internals, load balancing, preemption, real-time classes, energy-aware scheduling
Mastery of kernel synchronization: locking primitives, RCU, lock-free techniques, the ARM64 memory model and barrier semantics
Proven kernel performance-analysis skills: PMU counters, ftrace/perf, eBPF, lock contention and latency analysis
Strong ARM64 architecture grounding: exception levels, cache hierarchy and maintenance, TLBs, memory ordering